PIC16F818/819
5.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
“PICmicro
®
Mid-Range MCU Family Reference
Manual”
(DS33023).
Pin RA4 is multiplexed with the Timer0 module clock
input and with an analog input to become the RA4/AN4/
T0CKI pin. The RA4/AN4/T0CKI pin is a Schmitt
Trigger input and full CMOS output driver.
Pin RA5 is multiplexed with the Master Clear module
input. The RA5/MCLR/V
PP
pin is a Schmitt Trigger input.
Pin RA6 is multiplexed with the oscillator module input
and external oscillator output. Pin RA7 is multiplexed
with the oscillator module input and external oscillator
input. Pin RA6/OSC2/CLKO and pin RA7/OSC1/CLKI
are Schmitt Trigger inputs and full CMOS output drivers.
Pins RA<1:0> are multiplexed with analog inputs. Pins
RA<3:2> are multiplexed with analog inputs and V
REF
inputs. Pins RA<3:0> have TTL inputs and full CMOS
output drivers.
5.1
PORTA and the TRISA Register
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (=
1)
will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISA bit (=
0)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).
Note:
On a Power-on Reset, the pins
PORTA<4:0> are configured as analog
inputs and read as ‘0’.
EXAMPLE 5-1:
BANKSEL PORTA
CLRF
PORTA
INITIALIZING PORTA
;
;
;
;
;
;
;
;
;
;
;
select bank of PORTA
Initialize PORTA by
clearing output
data latches
Select Bank of ADCON1
Configure all pins
as digital inputs
Value used to
initialize data
direction
Set RA<7:0> as inputs
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified and then written to the port
data latch.
BANKSEL
MOVLW
MOVWF
MOVLW
ADCON1
0x06
ADCON1
0xFF
MOVWF
TRISA
TABLE 5-1:
Name
RA0/AN0
RA1/AN1
RA2/AN2/V
REF
-
RA3/AN3/V
REF
+
RA4/AN4/T0CKI
RA5/MCLR/V
PP
PORTA FUNCTIONS
Bit#
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Buffer
TTL
TTL
TTL
TTL
ST
ST
ST
Input/output or analog input.
Input/output or analog input.
Input/output, analog input or V
REF-
.
Input/output, analog input or V
REF+.
Input/output, analog input or external clock input for Timer0.
Input, Master Clear (Reset) or programming voltage input.
Input/output, connects to crystal or resonator, oscillator output or 1/4 the
frequency of OSC1 and denotes the instruction cycle in RC mode.
Function
RA6/OSC2/CLKO
RA7/OSC1/CLKI
ST/CMOS
(1)
Input/output, connects to crystal or resonator or oscillator input.
Legend:
TTL = TTL input, ST = Schmitt Trigger input
Note 1:
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
TABLE 5-2:
Address
05h
85h
9Fh
Legend:
Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
RA7
ADFM
Bit 6
RA6
ADCS2
Bit 5
RA5
—
Bit 4
RA4
—
Bit 3
RA3
Bit 2
RA2
Bit 1
RA1
Bit 0
RA0
PCFG0
Value on
POR, BOR
xxx0 0000
1111 1111
00-- 0000
Value on all
other Resets
uuu0 0000
1111 1111
00-- 0000
Name
PORTA
TRISA
ADCON1
TRISA7 TRISA6 TRISA5
(1)
PORTA Data Direction Register
PCFG3 PCFG2 PCFG1
x
= unknown,
u
= unchanged,
-
= unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
2004 Microchip Technology Inc.
DS39598E-page 39
MICROCHIP [ MICROCHIP TECHNOLOGY ]
