PIC16F818/819
The steps to write to EEPROM data memory are:
3.3
Reading Data EEPROM Memory
1. If step 10 is not implemented, check the WR bit
to see if a write is in progress.
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD
control bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available in the very next
cycle in the EEDATA register; therefore, it can be read
in the next instruction (see Example 3-1). EEDATA will
hold this value until another read or until it is written to
by the user (during a write operation).
2. Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
3. Write the 8-bit data value to be programmed in
the EEDATA register.
4. Clear the EEPGD bit to point to EEPROM data
memory.
The steps to reading the EEPROM data memory are:
5. Set the WREN bit to enable program operations.
6. Disable interrupts (if enabled).
1. Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
7. Execute the special five instruction sequence:
2. Clear the EEPGD bit to point to EEPROM data
memory.
• Write 55h to EECON2 in two steps (first to W,
then to EECON2)
3. Set the RD bit to start the read operation.
4. Read the data from the EEDATA register.
• Write AAh to EECON2 in two steps (first to W,
then to EECON2)
• Set the WR bit
EXAMPLE 3-1:
DATA EEPROM READ
8. Enable interrupts (if using interrupts).
BANKSEL EEADR
; Select Bank of EEADR
;
; Data Memory Address
; to read
9. Clear the WREN bit to disable program
operations.
MOVF
MOVWF
ADDR, W
EEADR
10. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set
(EEIF must be cleared by firmware). If step 1 is
not implemented, then firmware should check
for EEIF to be set, or WR to be clear, to indicate
the end of the program cycle.
BANKSEL EECON1
; Select Bank of EECON1
BCF
BSF
EECON1, EEPGD ; Point to Data memory
EECON1, RD
; EE Read
; Select Bank of EEDATA
; W = EEDATA
BANKSEL EEDATA
MOVF EEDATA, W
EXAMPLE 3-2:
DATA EEPROM WRITE
3.4
Writing to Data EEPROM Memory
BANKSEL EECON1
; Select Bank of
; EECON1
; Wait for write
; to complete
; Select Bank of
; EEADR
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then, the user must follow a
specific write sequence to initiate the write for each
byte.
BTFSC
GOTO
EECON1, WR
$-1
BANKSEL EEADR
MOVF
ADDR, W
;
MOVWF
EEADR
; Data Memory
; Address to write
;
; Data Memory Value
; to write
The write will not initiate if the write sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment (see Example 3-2).
MOVF
MOVWF
VALUE, W
EEDATA
BANKSEL EECON1
; Select Bank of
; EECON1
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times except when
updating EEPROM. The WREN bit is not cleared
by hardware
BCF
BSF
EECON1, EEPGD ; Point to DATA
; memory
EECON1, WREN ; Enable writes
BCF
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
; Disable INTs.
;
; Write 55h
;
; Write AAh
; Set WR bit to
; begin write
; Enable INTs.
MOVLW
MOVWF
MOVLW
MOVWF
BSF
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
BSF
BCF
INTCON, GIE
EECON1, WREN ; Disable writes
2004 Microchip Technology Inc.
DS39598E-page 27
MICROCHIP [ MICROCHIP ]
