PIC16F818/819
REGISTER 3-1:
EECON1: EEPROM ACCESS CONTROL REGISTER 1 (ADDRESS 18Ch)
R/W-x
U-0
—
U-0
—
R/W-x
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
EEPGD
WRERR
bit 7
bit 0
bit 7
EEPGD: Program/Data EEPROM Select bit
1= Accesses program memory
0= Accesses data memory
Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress.
bit 6-5
bit 4
Unimplemented: Read as ‘0’
FREE: EEPROM Forced Row Erase bit
1= Erase the program memory row addressed by EEADRH:EEADR on the next WR command
0= Perform write-only
bit 3
WRERR: EEPROM Error Flag bit
1= A write operation is prematurely terminated (any MCLR or any WDT Reset during normal
operation)
0= The write operation completed
bit 2
bit 1
WREN: EEPROM Write Enable bit
1= Allows write cycles
0= Inhibits write to the EEPROM
WR: Write Control bit
1= Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read, RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.
0= Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit S = Set only
U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set
‘0’ = Bit is cleared x = Bit is unknown
DS39598E-page 26
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
