PIC16F631/677/685/687/689/690
2.2.2.7
PIR2 Register
The PIR2 register contains the interrupt flag bits, as
shown in Register 2-7.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 2-7:
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0
OSFIF
bit 7
R/W-0
C2IF
R/W-0
C1IF
R/W-0
EEIF
U-0
—
U-0
—
U-0
—
U-0
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
OSFIF: Oscillator Fail Interrupt Flag bit
1= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0= System clock operating
C2IF: Comparator C2 Interrupt Flag bit
1= Comparator output (C2OUT bit) has changed (must be cleared in software)
0= Comparator output (C2OUT bit) has not changed
C1IF: Comparator C1 Interrupt Flag bit
1= Comparator output (C1OUT bit) has changed (must be cleared in software)
0= Comparator output (C1OUT bit) has not changed
EEIF: EE Write Operation Interrupt Flag bit
1= Write operation completed (must be cleared in software)
0= Write operation has not completed or has not started
Unimplemented: Read as ‘0’
DS41262D-page 42
© 2007 Microchip Technology Inc.
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