PIC16F72X/PIC16LF72X
4.0
INTERRUPTS
The PIC16F72X/PIC16LF72X device family features
an interruptible core, allowing certain events to
preempt normal program flow. An Interrupt Service
Routine (ISR) is used to determine the source of the
interrupt and act accordingly. Some interrupts can be
configured to wake the MCU from Sleep mode.
The PIC16F72X/PIC16LF72X device family has 12
interrupt sources, differentiated by corresponding
interrupt enable and flag bits:
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Timer0 Overflow Interrupt
External Edge Detect on INT Pin Interrupt
PORTB Change Interrupt
Timer1 Gate Interrupt
A/D Conversion Complete Interrupt
AUSART Receive Interrupt
AUSART Transmit Interrupt
SSP Event Interrupt
CCP1 Event Interrupt
Timer2 Match with PR2 Interrupt
Timer1 Overflow Interrupt
CCP2 Event Interrupt
A block diagram of the interrupt logic is shown in
FIGURE 4-1:
IOC-RB0
IOCB0
IOC-RB1
IOCB1
IOC-RB2
IOCB2
IOC-RB3
IOCB3
IOC-RB4
IOCB4
IOC-RB5
IOCB5
IOC-RB6
IOCB6
IOC-RB7
IOCB7
INTERRUPT LOGIC
SSPIF
SSPIE
TXIF
TXIE
RCIF
RCIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
ADIF
ADIE
TMR1GIF
TMR1GIE
CCP1IF
CCP1IE
CCP2IF
CCP2IE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
PEIE
GIE
Wake-up (If in Sleep mode)
(1)
Interrupt to CPU
Note 1:
Some peripherals depend upon the
system clock for operation. Since the
system clock is suspended during
Sleep, these peripherals will not wake
the part from Sleep. See
©
2009 Microchip Technology Inc.
DS41341E-page 43
MICROCHIP [ MICROCHIP TECHNOLOGY ]
