PIC16F72X/PIC16LF72X
3.0
RESETS
The PIC16F72X/PIC16LF72X differentiates between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
Power-on Reset (POR)
WDT Reset during normal operation
WDT Reset during Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
Brown-out Reset (BOR)
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal
operation. TO and PD bits are set or cleared differently
in different Reset situations, as indicated in Table 3-3.
These bits are used in software to determine the nature
of the Reset.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See
for pulse width specifications.
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
•
•
•
•
•
Power-on Reset (POR)
MCLR Reset
MCLR Reset during Sleep
WDT Reset
Brown-out Reset (BOR)
FIGURE 3-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
MCLRE
MCLR/V
PP
Sleep
WDT
Module
WDT
Time-out
Reset
POR
V
DD
Brown-out
(1)
Reset
BOREN
Power-on Reset
OST/PWRT
OST
10-bit Ripple Counter
OSC1/
CLKIN
PWRT
WDTOSC
11-bit Ripple Counter
Chip_Reset
Enable PWRT
Enable OST
Note
1:
Refer to the Configuration Word Register 1 (Register 8-1).
©
2009 Microchip Technology Inc.
DS41341E-page 33
MICROCHIP [ MICROCHIP TECHNOLOGY ]
