PIC16F72X/PIC16LF72X
12.0
TIMER1 MODULE WITH GATE
CONTROL
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Selectable Gate Source Polarity
Gate Toggle Mode
Gate Single-pulse Mode
Gate Value Status
Gate Event Interrupt
The Timer1 module is a 16-bit timer/counter with the
following features:
16-bit timer/counter register pair (TMR1H:TMR1L)
Programmable internal or external clock source
3-bit prescaler
Dedicated LP oscillator circuit
Synchronous or asynchronous operation
Multiple Timer1 gate (count enable) sources
Interrupt on overflow
Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Special Event Trigger (with CCP)
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FIGURE 12-1:
T1GSS<1:0>
TIMER1 BLOCK DIAGRAM
T1G
From Timer0
Overflow
From Timer2
Match PR2
From WDT
Overflow
00
01
10
D
11
TMR1ON
T1GPOL
Set flag bit
TMR1IF on
Overflow
T1GTM
CK
R
Q
T1GGO/DONE
Q
1
T1G_IN
0
T1GSPM
0
T1GVAL
Single Pulse
Acq. Control
1
Q1
D
EN
Q
RD
T1GCON
Set
TMR1GIF
Data Bus
Interrupt
det
TMR1GE
TMR1ON
TMR1
(2)
TMR1H
TMR1L
Q
EN
T1CLK
D
1
TMR1CS<1:0>
T1SYNC
11
Prescaler
1, 2, 4, 8
10
0
F
OSC
Internal
Clock
F
OSC
/4
Internal
Clock
01
2
T1CKPS<1:0>
F
OSC
/2
Internal
Clock
0
Synchronized
clock input
T1OSO/T1CKI
OUT
T1OSC
1
Cap. Sensing
Oscillator
Synchronize
(3)
det
T1OSI
EN
T1OSCEN
(1)
Sleep input
00
T1CKI
Note 1:
ST Buffer is high speed type when using T1CKI.
2:
Timer1 register increments on rising edge.
3:
Synchronize does not operate while in Sleep.
©
2009 Microchip Technology Inc.
DS41341E-page 115
MICROCHIP [ MICROCHIP TECHNOLOGY ]
