PIC16F688
FIGURE 3-9:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Test
Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
TABLE 3-2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Value on
Value on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
POR, BOR
(1)
Resets
(2)
CONFIG
CPD
GIE
—
CP
PEIE
IRCF2
—
MCLRE PWRTE
WDTE
RAIE
OSTS
TUN3
C1IE
FOSC2
T0IF
FOSC1
INTF
LTS
FOSC0
RAIF
—
—
INTCON
OSCCON
OSCTUNE
PIE1
T0IE
IRCF1
—
INTE
IRCF0
TUN4
C2IE
0000 000x 0000 000x
-110 x000 -110 x000
---0 0000 ---u uuuu
0000 0000 0000 0000
0000 0000 0000 0000
HTS
SCS
—
TUN2
OSFIE
OSFIF
TUN1
TXIE
TXIF
TUN0
EEIE
EEIF
ADIE
ADIF
RCIE
RCIF
TMR1IE
TMR1IF
PIR1
C2IF
C1IF
Legend:
x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: See Configuration Word register (CONFIG) for operation of all register bits.
DS41203D-page 32
© 2007 Microchip Technology Inc.
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