PIC16F688
This will occur regardless of VDD slew rate. A Reset is
not insured to occur if VDD falls below VBOD for less
than parameter (TBOD).
11.2.4
BROWN-OUT RESET (BOR)
The BOREN0 and BOREN1 bits in the Configuration
Word register selects one of four BOR modes. Two
modes have been added to allow software or hardware
control of the BOR enable. When BOREN<1:0> = 01,
the SBOREN bit of the PCON register enables/disables
the BOR, allowing it to be controlled in software. By
selecting BOREN<1:0>, the BOR is automatically
disabled in Sleep to conserve power and enabled on
wake-up. In this mode, the SBOREN bit is disabled.
See Register 11-1 for the Configuration Word
definition.
On any Reset (Power-on, Brown-out Reset, Watchdog
Timer, etc.), the chip will remain in Reset until VDD rises
above VBOD (see Figure 11-3). The Power-up Timer
will now be invoked, if enabled and will keep the chip in
Reset an additional 64 ms.
Note:
The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word
register.
If VDD drops below VBOD while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOD, the Power-up Timer will execute a
64 ms Reset.
If VDD falls below VBOD for greater than parameter
(TBOD) (see Section 14.0 “Electrical Specifica-
tions”), the Brown-out situation will reset the device.
FIGURE 11-3:
BROWN-OUT SITUATIONS
VDD
VBOD
Internal
Reset
(1)
64 ms
VDD
VBOD
Internal
Reset
< 64 ms
(1)
64 ms
VDD
VBOD
Internal
Reset
(1)
64 ms
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.
DS41203D-page 114
© 2007 Microchip Technology Inc.
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