PIC16F688
BTFSC
Bit Test, Skip if Clear
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] BTFSC f,b
Syntax:
[ label ] CLRWDT
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
Operation:
None
00h → WDT
0 → WDT prescaler,
1 → TO
Operation:
skip if (f<b>) = 0
Status Affected: None
1 → PD
Description:
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
Status Affected: TO, PD
If bit ‘b’, in register ‘f’, is ‘0’, the
next instruction is discarded, and
a NOPis executed instead, making
this a 2-cycle instruction.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT.
Status bits TO and PD are set.
CALL
Call Subroutine
COMF
Complement f
Syntax:
[ label ] CALL k
0 ≤ k ≤ 2047
Syntax:
[ label ] COMF f,d
0 ≤ f ≤ 127
Operands:
Operation:
Operands:
d
[0,1]
(PC)+ 1→ TOS,
k → PC<10:0>,
Operation:
(f) → (destination)
(PCLATH<4:3>) → PC<12:11>
Status Affected:
Description:
Z
Status Affected: None
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
Description:
Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit
immediate address is loaded into
PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALLis a two-cycle instruction.
DECF
Decrement f
CLRF
Clear f
Syntax:
[ label ] DECF f,d
0 ≤ f ≤ 127
Syntax:
[ label ] CLRF
0 ≤ f ≤ 127
f
Operands:
Operands:
Operation:
d
[0,1]
00h → (f)
1 → Z
Operation:
(f) - 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
The contents of register ‘f’ are
cleared and the Z bit is set.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
Operation:
None
00h → (W)
1 → Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z)
is set.
DS41203B-page 122
Preliminary
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
