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PIC16F687-I/ML 参数 Datasheet PDF下载

PIC16F687-I/ML图片预览
型号: PIC16F687-I/ML
PDF下载: 下载PDF文件 查看货源
内容描述: 20引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 294 页 / 5272 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F631/677/685/687/689/690  
2.2.2.6  
PIR1 Register  
The PIR1 register contains the interrupt flag bits, as  
shown in Register 2-6.  
Note:  
Interrupt flag bits are set when an interrupt  
condition occurs, regardless of the state of  
its corresponding enable bit or the global  
enable bit, GIE of the INTCON register.  
User software should ensure the  
appropriate interrupt flag bits are clear  
prior to enabling an interrupt.  
REGISTER 2-6:  
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1  
U-0  
R/W-0  
ADIF(5)  
R-0  
RCIF(3)  
R-0  
TXIF(3)  
R/W-0  
SSPIF(4)  
R/W-0  
CCP1IF(2)  
R/W-0  
TMR2IF(1)  
R/W-0  
TMR1IF  
bit 7  
bit 0  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
bit 7  
bit 6  
Unimplemented: Read as ‘0’  
ADIF: A/D Converter Interrupt Flag bit(5)  
1= A/D conversion complete (must be cleared in software)  
0= A/D conversion has not completed or has not been started  
bit 5  
bit 4  
bit 3  
bit 2  
RCIF: EUSART Receive Interrupt Flag bit(3)  
1= The EUSART receive buffer is full (cleared by reading RCREG)  
0= The EUSART receive buffer is not full  
TXIF: EUSART Transmit Interrupt Flag bit(3)  
1= The EUSART transmit buffer is empty (cleared by writing to TXREG)  
0= The EUSART transmit buffer is full  
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit(4)  
1= The Transmission/Reception is complete (must be cleared in software)  
0= Waiting to Transmit/Receive  
CCP1IF: CCP1 Interrupt Flag bit(2)  
Capture mode:  
1= A TMR1 register capture occurred (must be cleared in software)  
0= No TMR1 register capture occurred  
Compare mode:  
1= A TMR1 register compare match occurred (must be cleared in software)  
0= No TMR1 register compare match occurred  
PWM mode:  
Unused in this mode  
bit 1  
bit 0  
TMR2IF: Timer2 to PR2 Interrupt Flag bit(1)  
1= A Timer2 to PR2 match occurred (must be cleared in software)  
0= No Timer2 to PR2 match occurred  
TMR1IF: Timer1 Overflow Interrupt Flag bit  
1= The TMR1 register overflowed (must be cleared in software)  
0= The TMR1 register did not overflow  
Note 1: PIC16F685/PIC16F690 only.  
2: PIC16F685/PIC16F689/PIC16F690 only.  
3: PIC16F687/PIC16F689/PIC16F690 only.  
4: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.  
5: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.  
© 2007 Microchip Technology Inc.  
DS41262D-page 41  
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