PIC16F631/677/685/687/689/690
2.2.2.5
PIE2 Register
The PIE2 register contains the interrupt enable bits, as
shown in Register 2-5.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 2-5:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0
OSFIE
bit 7
R/W-0
C2IE
R/W-0
C1IE
R/W-0
EEIE
U-0
—
U-0
—
U-0
—
U-0
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
OSFIE: Oscillator Fail Interrupt Enable bit
1= Enables oscillator fail interrupt
0= Disables oscillator fail interrupt
C2IE: Comparator C2 Interrupt Enable bit
1= Enables Comparator C2 interrupt
0= Disables Comparator C2 interrupt
C1IE: Comparator C1 Interrupt Enable bit
1= Enables Comparator C1 interrupt
0= Disables Comparator C1 interrupt
EEIE: EE Write Operation Interrupt Enable bit
1= Enables write operation interrupt
0= Disables write operation interrupt
Unimplemented: Read as ‘0’
DS41262D-page 40
© 2007 Microchip Technology Inc.
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