欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC16F685-I/SS 参数 Datasheet PDF下载

PIC16F685-I/SS图片预览
型号: PIC16F685-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 20引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 294 页 / 5272 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC16F685-I/SS的Datasheet PDF文件第83页浏览型号PIC16F685-I/SS的Datasheet PDF文件第84页浏览型号PIC16F685-I/SS的Datasheet PDF文件第85页浏览型号PIC16F685-I/SS的Datasheet PDF文件第86页浏览型号PIC16F685-I/SS的Datasheet PDF文件第88页浏览型号PIC16F685-I/SS的Datasheet PDF文件第89页浏览型号PIC16F685-I/SS的Datasheet PDF文件第90页浏览型号PIC16F685-I/SS的Datasheet PDF文件第91页  
PIC16F631/677/685/687/689/690  
TRISA5 and TRISA4 bits are set when the Timer1  
oscillator is enabled. RA5 and RA4 bits read as ‘0’ and  
TRISA5 and TRISA4 bits read as ‘1’.  
6.2.1  
INTERNAL CLOCK SOURCE  
When the internal clock source is selected the  
TMR1H:TMR1L register pair will increment on multiples  
of FOSC as determined by the Timer1 prescaler.  
Note:  
The oscillator requires a start-up and  
stabilization time before use. Thus,  
T1OSCEN should be set and a suitable  
delay observed prior to enabling Timer1.  
6.2.2  
EXTERNAL CLOCK SOURCE  
When the external clock source is selected, the Timer1  
module may work as a timer or a counter.  
6.5  
Timer1 Operation in  
Asynchronous Counter Mode  
When counting, Timer1 is incremented on the rising  
edge of the external clock input T1CKI. In addition, the  
Counter mode clock can be synchronized to the  
microcontroller system clock or run asynchronously.  
If control bit T1SYNC of the T1CON register is set, the  
external clock input is not synchronized. The timer  
increments asynchronously to the internal phase  
clocks. If external clock source is selected then the  
timer will continue to run during Sleep and can  
generate an interrupt on overflow, which will wake-up  
the processor. However, special precautions in  
software are needed to read/write the timer (see  
Section 6.5.1 “Reading and Writing Timer1 in  
Asynchronous Counter Mode”).  
If an external clock oscillator is needed (and the  
microcontroller is using the INTOSC without CLKOUT),  
Timer1 can use the LP oscillator as a clock source.  
Note:  
In Counter mode, a falling edge must be  
registered by the counter prior to the first  
incrementing rising edge after any one or  
more of the following conditions:  
• Timer1 enabled after POR reset  
• Write to TMR1H or TMR1L  
• Timer1 is disabled  
Note:  
When switching from synchronous to  
asynchronous operation, it is possible to  
skip an increment. When switching from  
asynchronous to synchronous operation,  
it is possible to produce an additional  
increment.  
• Timer1 is disabled (TMR1ON 0) when  
T1CKI is high then Timer1 is enabled  
(TMR1ON=1) when T1CKI is low.  
Note:  
See Figure 6-2  
6.5.1  
READING AND WRITING TIMER1 IN  
ASYNCHRONOUS COUNTER  
MODE  
6.3  
Timer1 Prescaler  
Timer1 has four prescaler options allowing 1, 2, 4 or 8  
divisions of the clock input. The T1CKPS bits of the  
T1CON register control the prescale counter. The  
prescale counter is not directly readable or writable;  
however, the prescaler counter is cleared upon a write to  
TMR1H or TMR1L.  
Reading TMR1H or TMR1L while the timer is running  
from an external asynchronous clock will ensure a valid  
read (taken care of in hardware). However, the user  
should keep in mind that reading the 16-bit timer in two  
8-bit values itself, poses certain problems, since the  
timer may overflow between the reads.  
For writes, it is recommended that the user simply stop  
the timer and write the desired values. A write  
contention may occur by writing to the timer registers,  
while the register is incrementing. This may produce an  
unpredictable value in the TMR1H:TMR1L register pair.  
6.4  
Timer1 Oscillator  
A low-power 32.768 kHz crystal oscillator is built-in  
between pins OSC1 (input) and OSC2 (amplifier  
output). The oscillator is enabled by setting the  
T1OSCEN control bit of the T1CON register. The  
oscillator will continue to run during Sleep.  
6.6  
Timer1 Gate  
The Timer1 oscillator is shared with the system LP  
oscillator. Thus, Timer1 can use this mode only when  
the primary system clock is derived from the internal  
oscillator or when the oscillator is in the LP mode. The  
user must provide a software time delay to ensure  
proper oscillator start-up.  
Timer1 gate source is software configurable to be the  
T1G pin or the output of Comparator C2. This allows the  
device to directly time external events using T1G or  
analog events using Comparator C2. See the  
CM2CON1 register (Register 8-3) for selecting the  
Timer1 gate source. This feature can simplify the  
software for a Delta-Sigma A/D converter and many  
other applications. For more information on Delta-Sigma  
A/D converters, see the Microchip web site  
(www.microchip.com).  
© 2007 Microchip Technology Inc.  
DS41262D-page 85  
 复制成功!