PIC16F631/677/685/687/689/690
When changing the prescaler assignment from the
WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 5-2).
5.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignment is controlled by the PSA bit of the OPTION
register. To assign the prescaler to Timer0, the PSA bit
must be cleared to a ‘0’.
EXAMPLE 5-2:
CHANGING PRESCALER
(WDT → TIMER0)
CLRWDT
;Clear WDT and
;prescaler
;
BANKSEL OPTION_REG
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION register.
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.
MOVLW
ANDWF
IORLW
MOVWF
b’11110000’ ;Mask TMR0 select and
OPTION_REG,W ; prescaler bits
b’00000011’ ;Set prescale to 1:16
OPTION_REG
;
5.1.4
TIMER0 INTERRUPT
The prescaler is not readable or writable. When the
prescaler is assigned to the Timer0 module, all
instructions writing to the TMR0 register will clear the
prescaler.
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
TMR0 register overflows, regardless of whether or not
the Timer0 interrupt is enabled. The T0IF bit must be
cleared in software. The Timer0 interrupt enable is the
T0IE bit of the INTCON register.
When the prescaler is assigned to WDT, a CLRWDT
instruction will clear the prescaler along with the WDT.
5.1.3.1
Switching Prescaler Between
Timer0 and WDT Modules
Note:
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
As a result of having the prescaler assigned to either
Timer0 or the WDT, it is possible to generate an
unintended device Reset when switching prescaler
values. When changing the prescaler assignment from
Timer0 to the WDT module, the instruction sequence
shown in Example 5-1, must be executed.
5.1.5
USING TIMER0 WITH AN
EXTERNAL CLOCK
When Timer0 is in Counter mode, the synchronization
of the T0CKI input and the Timer0 register is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, the
high and low periods of the external clock source must
meet the timing requirements as shown in
Section 17.0 “Electrical Specifications”.
EXAMPLE 5-1:
CHANGING PRESCALER
(TIMER0 → WDT)
BANKSEL TMR0
CLRWDT
CLRF
;
;Clear WDT
TMR0
;Clear TMR0 and
;
;
prescaler
BANKSEL OPTION_REG
BSF
OPTION_REG,PSA ;Select WDT
CLRWDT
;
;
MOVLW
ANDWF
IORLW
MOVWF
b’11111000’
OPTION_REG,W
b’00000101’
OPTION_REG
;Mask prescaler
bits
;Set WDT prescaler
to 1:32
;
;
DS41262D-page 82
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
