PIC16F631/677/685/687/689/690
Timer2
Associated registers....................................................92
Timers
Timer1
T1CON................................................................88
Timer2
T2CON................................................................92
Timing Diagrams
A/D Conversion.........................................................253
Timing Parameter Symbology .......................................... 237
Timing Requirements
2
I C Bus Data............................................................. 251
I2C Bus Start/Stop Bits............................................. 250
SPI Mode.................................................................. 249
TRISA
Registers .................................................................... 59
TRISA Register................................................................... 59
TRISB
A/D Conversion (Sleep Mode) ..................................254
Asynchronous Reception ..........................................156
Asynchronous Transmission.....................................152
Asynchronous Transmission (Back to Back) ............152
Auto Wake-up Bit (WUE) During Normal Operation .166
Auto Wake-up Bit (WUE) During Sleep ....................167
Automatic Baud Rate Calculator...............................165
Brown-out Reset (BOR)............................................241
Brown-out Reset Situations ......................................198
CLKOUT and I/O.......................................................240
Clock Synchronization ..............................................192
Clock Timing .............................................................238
Comparator Output .....................................................93
Enhanced Capture/Compare/PWM (ECCP).............244
EUSART Synchronous Receive (Master/Slave) .......246
EUSART Synchronous Transmission
Registers .................................................................... 69
TRISB Register................................................................... 70
TRISC
Registers .................................................................... 76
TRISC Register................................................................... 76
Two-Speed Clock Start-up Mode........................................ 55
TXREG ............................................................................. 151
TXSTA Register................................................................ 158
BRGH Bit .................................................................. 161
U
UA..................................................................................... 176
Ultra Low-Power Wake-up.............. 14, 16, 18, 20, 22, 60, 63
Update Address bit, UA .................................................... 176
V
Voltage Reference (VR)
Specifications ........................................................... 245
Voltage Reference. See Comparator
Voltage Reference (CVREF)
Voltage References
Associated registers ................................................. 106
VP6 Stabilization ...................................................... 105
VRCON Register .............................................................. 106
VREF. SEE ADC Reference Voltage
(Master/Slave)...................................................246
Fail-Safe Clock Monitor (FSCM).................................58
Full-Bridge PWM Output ...........................................138
Half-Bridge PWM Output .................................. 136, 143
2
I C Bus Data.............................................................250
2
I C Bus Start/Stop Bits..............................................249
2
I C Reception (7-bit Address)...................................186
2
I C Slave Mode (Transmission, 10-bit Address).......190
2
I C Slave Mode with SEN = 0 (Reception,
10-bit Address)..................................................188
I C Transmission (7-bit Address)..............................189
W
2
Wake-up on Break............................................................ 166
Wake-up Using Interrupts................................................. 210
Watchdog Timer (WDT).................................................... 208
Associated registers ................................................. 209
Clock Source ............................................................ 208
Modes....................................................................... 208
Period ....................................................................... 208
Specifications ........................................................... 242
WCOL bit .......................................................................... 177
WDTCON Register ........................................................... 209
WPUA Register................................................................... 62
WPUB Register................................................................... 70
Write Collision Detect bit (WCOL) .................................... 177
WWW Address ................................................................. 289
WWW, On-Line Support ....................................................... 8
INT Pin Interrupt........................................................206
Internal Oscillator Switch Timing.................................54
PWM Auto-shutdown
Auto-restart Enabled.........................................142
Firmware Restart ..............................................142
PWM Direction Change ............................................139
PWM Direction Change at Near 100% Duty Cycle ...140
PWM Output (Active-High)........................................134
PWM Output (Active-Low) ........................................135
Reset, WDT, OST and Power-up Timer ...................241
Send Break Character Sequence .............................168
Slave Synchronization ..............................................181
SPI Master Mode (CKE = 1, SMP = 1) .....................247
SPI Mode (Master Mode)..........................................180
SPI Mode (Slave Mode with CKE = 0)......................182
SPI Mode (Slave Mode with CKE = 1)......................182
SPI Slave Mode (CKE = 0) .......................................248
SPI Slave Mode (CKE = 1) .......................................248
Synchronous Reception (Master Mode, SREN) .......172
Synchronous Transmission.......................................170
Synchronous Transmission (Through TXEN) ...........170
Time-out Sequence
Case 1...............................................................200
Case 2...............................................................200
Case 3...............................................................200
Timer0 and Timer1 External Clock ...........................243
Timer1 Incrementing Edge..........................................87
Two Speed Start-up ....................................................56
Wake-up from Interrupt .............................................211
DS41262D-page 288
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MICROCHIP [ MICROCHIP ]
