PIC16F631/677/685/687/689/690
EEADR (EEPROM Address) .................................... 120
SPI Mode.................................................................. 175, 181
Associated Registers................................................ 183
Bus Mode Compatibility............................................ 183
Effects of a Reset ..................................................... 183
Enabling SPI I/O....................................................... 179
Master Mode............................................................. 180
Master/Slave Connection ......................................... 179
Serial Clock (SCK pin).............................................. 175
Serial Data In (SDI pin)............................................. 175
Serial Data Out (SDO pin)........................................ 175
Slave Select.............................................................. 175
Slave Select Synchronization................................... 181
Sleep Operation........................................................ 183
SPI Clock.................................................................. 180
Typical Connection................................................... 179
SRCON Register .............................................................. 103
SSP
EECON1 (EEPROM Control 1)................................. 121
EEDAT (EEPROM Data) .......................................... 120
EEDATH (EEPROM Data)........................................ 120
INTCON (Interrupt Control)......................................... 38
IOCA (Interrupt-on-Change PORTA).......................... 62
IOCB (Interrupt-on-Change PORTB).......................... 70
OPTION_REG (OPTION) ..................................... 37, 83
OSCCON (Oscillator Control) ..................................... 48
OSCTUNE (Oscillator Tuning).................................... 52
PCON (Power Control Register)................................. 43
PCON (Power Control) ............................................. 199
PIE1 (Peripheral Interrupt Enable 1)........................... 39
PIE2 (Peripheral Interrupt Enable 2)........................... 40
PIR1 (Peripheral Interrupt Register 1) ........................ 41
PIR2 (Peripheral Interrupt Request 2) ........................ 42
PORTA........................................................................ 59
PORTB........................................................................ 69
PORTC ....................................................................... 76
PSTRCON (Pulse Steering Control)......................... 145
PWMxCON (Enhanced PWM Control) ..................... 144
RCSTA (Receive Status and Control)....................... 159
Reset Values............................................................. 201
Reset Values (special registers) ............................... 203
Special Function Register Map
Overview
SPI Master/Slave Connection................................... 179
2
SSP I C Operation ........................................................... 184
Slave Mode............................................................... 184
SSP Module
Clock Synchronization and the CKP Bit ................... 191
SPI Master Mode...................................................... 180
SPI Slave Mode........................................................ 181
SSPBUF ................................................................... 180
SSPSR ..................................................................... 180
SSPCON Register ............................................................ 177
SSPEN bit......................................................................... 177
SSPM bits......................................................................... 177
SSPMSK Register ............................................................ 187
SSPOV bit ........................................................................ 177
SSPSTAT Register........................................................... 176
STATUS Register ............................................................... 36
Synchronous Serial Port Enable bit (SSPEN) .................. 177
Synchronous Serial Port Mode Select bits (SSPM).......... 177
Synchronous Serial Port. See SSP
PIC16F677.......................................................... 28
PIC16F685.................................................... 27, 29
PIC16F687/689................................................... 30
PIC16F690.......................................................... 31
Special Function Registers ......................................... 26
Special Register Summary
Bank 0................................................................. 32
Bank 1................................................................. 33
Bank 2................................................................. 34
Bank 3................................................................. 35
SRCON (SR Latch Control) ...................................... 103
SSPCON (Sync Serial Port Control) Register........... 177
SSPMSK (SSP Mask)............................................... 187
SSPSTAT (Sync Serial Port Status) Register........... 176
STATUS...................................................................... 36
T1CON........................................................................ 88
T2CON........................................................................ 92
TRISA (Tri-State PORTA)........................................... 59
TRISB (Tri-State PORTB)........................................... 70
TRISC (Tri-State PORTC) .......................................... 76
TXSTA (Transmit Status and Control) ...................... 158
VRCON (Voltage Reference Control) ....................... 106
WDTCON (Watchdog Timer Control) ....................... 209
WPUA (Weak Pull-Up PORTA) .................................. 62
WPUB (Weak Pull-up PORTB)................................... 70
Reset................................................................................. 196
Revision History................................................................ 281
T
T1CON Register ................................................................. 88
T2CON Register ................................................................. 92
Thermal Considerations.................................................... 236
Time-out Sequence .......................................................... 199
Timer0 ................................................................................ 81
Associated Registers.................................................. 83
External Clock ............................................................ 82
Interrupt ...................................................................... 83
Operation.............................................................. 81, 84
Specifications ........................................................... 243
T0CKI ......................................................................... 82
Timer1 ................................................................................ 84
Associated registers ................................................... 89
Asynchronous Counter Mode..................................... 85
Reading and Writing........................................... 85
Interrupt ...................................................................... 86
Modes of Operation.................................................... 84
Operation During Sleep.............................................. 86
Oscillator..................................................................... 85
Prescaler .................................................................... 85
Specifications ........................................................... 243
Timer1 Gate
S
S (Start) bit........................................................................ 176
Shoot-through Current ...................................................... 143
Slave Select Synchronization ........................................... 181
Sleep................................................................................. 210
Wake-up.................................................................... 210
Wake-up Using Interrupts ......................................... 210
SMP bit ............................................................................. 176
Software Simulator (MPLAB SIM)..................................... 224
SPBRG ............................................................................. 161
SPBRGH........................................................................... 161
Special Event Trigger........................................................ 111
Special Function Registers ................................................. 26
Inverting Gate..................................................... 86
Selecting Source ........................................ 85, 101
Synchronizing COUT w/Timer1........................ 101
TMR1H Register......................................................... 84
TMR1L Register ......................................................... 84
© 2007 Microchip Technology Inc.
DS41262D-page 287
MICROCHIP [ MICROCHIP ]
