PIC16F631/677/685/687/689/690
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
12.4.2
SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for Synchronous slave operation:
1. The first character will immediately transfer to
the TSR register and transmit.
• SYNC = 1
2. The second word will remain in TXREG register.
3. The TXIF bit will not be set.
• CSRC = 0
• SREN = 0(for transmit); SREN = 1(for receive)
• CREN = 0(for transmit); CREN = 1(for receive)
• SPEN = 1
4. After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
5. If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the interrupt service routine.
12.4.2.2
Synchronous Slave Transmission
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Clear the CREN and SREN bits.
12.4.2.1
EUSART Synchronous Slave
Transmit
3. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
The operation of the Synchronous Master and Slave
modes are identical (see Section 12.4.1.3
“Synchronous Master Transmission”), except in the
4. If 9-bit transmission is desired, set the TX9 bit.
5. Enable transmission by setting the TXEN bit.
case of the Sleep mode.
6. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
7. Start transmission by writing the Least
Significant 8 bits to the TXREG register.
TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCTL ABDOVF RCIDL
—
SCKP
INTE
TXIE
TXIF
BRG16
RABIE
SSPIE
SSPIF
—
WUE
INTF
ABDEN 01-0 0-00 01-0 0-00
RABIF 0000 000x 0000 000x
INTCON
PIE1
GIE
—
PEIE
ADIE
ADIF
T0IE
RCIE
RCIF
T0IF
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
0000 0000 0000 0000
PIR1
—
RCREG
RCSTA
SPBRG
SPBRGH
TRISB
EUSART Receive Data Register
SPEN
BRG7
BRG15
RX9
BRG6
BRG14
SREN
BRG5
CREN
BRG4
ADDEN
BRG3
FERR
BRG2
BRG10
OERR
BRG1
BRG9
RX9D
BRG0
BRG8
0000 000x 0000 000x
0000 0000 0000 0000
0000 0000 0000 0000
1111 ---- 1111 ----
0000 0000 0000 0000
0000 0010 0000 0010
BRG13
BRG12
BRG11
TRISB7 TRISB6 TRISB5 TRISB4
EUSART Transmit Data Register
TXREG
TXSTA
Legend:
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
x= unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.
© 2007 Microchip Technology Inc.
DS41262D-page 173
MICROCHIP [ MICROCHIP ]
