PIC16F631/677/685/687/689/690
FIGURE 12-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
‘0’
‘0’
CREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
TABLE 12-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCTL ABDOVF RCIDL
—
SCKP
INTE
TXIE
TXIF
BRG16
RABIE
SSPIE
SSPIF
—
WUE
INTF
ABDEN 01-0 0-00 01-0 0-00
RABIF 0000 000x 0000 000x
INTCON
PIE1
GIE
—
PEIE
ADIE
ADIF
T0IE
RCIE
RCIF
T0IF
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
0000 0000 0000 0000
PIR1
—
RCREG
RCSTA
SPBRG
SPBRGH
TRISB
EUSART Receive Data Register
SPEN
BRG7
BRG15
RX9
BRG6
BRG14
SREN
BRG5
CREN
BRG4
ADDEN
BRG3
FERR
BRG2
OERR
BRG1
BRG9
RX9D
BRG0
BRG8
0000 000x 0000 000x
0000 0000 0000 0000
0000 0000 0000 0000
1111 ---- 1111 ----
0000 0000 0000 0000
0000 0010 0000 0010
BRG13
BRG12
BRG11
BRG10
TRISB7 TRISB6 TRISB5 TRISB4
EUSART Transmit Data Register
TXREG
TXSTA
Legend:
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
x= unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
DS41262D-page 172
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
