PIC16F5X
FIGURE 2-1:
Flash
512 X 12 (F54)
2048 X 12(F57)
2048 x 12(F59)
12
Instruction
Register
9
12
8
Instruction
Decoder
Direct Address
Direct RAM
Address
6
Option Reg.
From W
5
8
Literals
STATUS
TMR0
Data Bus
ALU
From W
4
TRISA
4
PORTA
4
“TRIS 5”
RA<3:0>
“TRIS 6”
RB<7:0>
8
From W
8
TRISB
8
PORTB
From W
8
TRISC
8
SFR
8
W
5-7
“Option”
General
Purpose
Register
File
(SRAM)
25, 72 or 134
Bytes
WDT
Time-out
WDT/TMR0
Prescaler
CLKOUT
PIC16F5X SERIES BLOCK DIAGRAM
9-11
9-11
PC
Watchdog
Timer
“Code-
Protect”
Stack 1
Stack 2
T0CKI
Pin
Configuration Word
“Disable”
OSC1 OSC2 MCLR
“Osc
Select”
2
Oscillator/
Timing &
Control
“Sleep”
PORTC
8
8
“TRIS 7”
RC<7:0>
PIC16F57/59
only
From W
8
4
TRISE
PORTE
4
“TRIS 9”
RE<7:4>
PIC16F59
only
From W
8
TRISD
8
PORTD
8
“TRIS 8”
RD<7:0>
PIC16F59
only
DS41213D-page 8
©
2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
