PIC16F87X
TMR0 .................................................................................17
TMR0 Register ...................................................................15
TMR1CS bit ........................................................................51
TMR1H ...............................................................................17
TMR1H Register ................................................................15
TMR1L ...............................................................................17
TMR1L Register .................................................................15
TMR1ON bit .......................................................................51
TMR2 .................................................................................17
TMR2 Register ...................................................................15
TMR2ON bit .......................................................................55
TOUTPS0 bit ......................................................................55
TOUTPS1 bit ......................................................................55
TOUTPS2 bit ......................................................................55
TOUTPS3 bit ......................................................................55
TRISA .................................................................................17
TRISA Register ..................................................................16
TRISB .................................................................................17
TRISB Register ..................................................................16
TRISC ................................................................................17
TRISC Register ..................................................................16
TRISD ................................................................................17
TRISD Register ..................................................................16
TRISE .................................................................................17
TRISE Register ............................................................ 16, 36
IBF Bit ........................................................................36
IBOV Bit .....................................................................36
OBF Bit ......................................................................36
PSPMODE Bit ................................................ 35, 36, 38
TXREG ...............................................................................17
TXSTA ................................................................................17
TXSTA Register .................................................................95
BRGH Bit ...................................................................95
CSRC Bit ....................................................................95
SYNC Bit ....................................................................95
TRMT Bit ....................................................................95
TX9 Bit .......................................................................95
TX9D Bit .....................................................................95
TXEN Bit ....................................................................95
RCSTA Register ........................................................ 96
Receive Block Diagram ........................................... 101
Receive Data, 9th bit (RX9D Bit) ............................... 96
Receive Enable, 9-bit (RX9 Bit) ................................. 96
Serial Port Enable (SPEN Bit) ............................. 95, 96
Single Receive Enable (SREN Bit) ............................ 96
Synchronous Master Mode ...................................... 105
Synchronous Master Reception ............................... 107
Synchronous Master Transmission ......................... 105
Synchronous Slave Mode ........................................ 108
Transmit Block Diagram ............................................ 99
Transmit Data, 9th Bit (TX9D) ................................... 95
Transmit Enable (TXEN Bit) ...................................... 95
Transmit Enable, Nine-bit (TX9 Bit) ........................... 95
Transmit Shift Register Status (TRMT Bit) ................ 95
TXSTA Register ......................................................... 95
W
Wake-up from SLEEP .............................................. 121, 134
Interrupts ......................................................... 127, 128
MCLR Reset ............................................................ 128
Timing Diagram ....................................................... 135
WDT Reset .............................................................. 128
Watchdog Timer (WDT) ........................................... 121, 133
Block Diagram ......................................................... 133
Enable (WDTE Bit) .................................................. 133
Programming Considerations .................................. 133
RC Oscillator ............................................................ 133
Time-out Period ....................................................... 133
WDT Reset, Normal Operation ................ 125, 127, 128
WDT Reset, SLEEP ................................. 125, 127, 128
Waveform for General Call Address Sequence ................. 74
WCOL .................................................. 65, 79, 81, 83, 85, 86
WCOL Status Flag ............................................................. 79
Write Collision Detect bit, WCOL ....................................... 65
WWW, On-Line Support ...................................................... 4
U
UA ......................................................................................64
Universal Synchronous Asynchronous Receiver
Transmitter (USART)
Asynchronous Receiver
Setting Up Reception .......................................103
Timing Diagram ................................................104
Update Address, UA ..........................................................64
USART ...............................................................................95
Asynchronous Mode ..................................................99
Receive Block Diagram ....................................103
Asynchronous Receiver ...........................................101
Asynchronous Reception .........................................102
Asynchronous Transmitter .........................................99
Baud Rate Generator (BRG) ......................................97
Baud Rate Formula ............................................97
Baud Rates, Asynchronous Mode (BRGH=0) ...98
High Baud Rate Select (BRGH Bit) ....................95
Sampling ............................................................97
Clock Source Select (CSRC Bit) ................................95
Continuous Receive Enable (CREN Bit) ....................96
Framing Error (FERR Bit) ..........................................96
Mode Select (SYNC Bit) ............................................95
Overrun Error (OERR Bit) ..........................................96
RC6/TX/CK Pin ........................................................7, 8
RC7/RX/DT Pin ........................................................7, 8
DS30292B-page 190
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
