PIC16F87X
SSP Module
SPI Master Mode ....................................................... 68
Timers
Timer0
SPI Slave Mode ......................................................... 69
SSPCON1 Register ................................................... 71
SSP Overflow Detect bit, SSPOV ...................................... 72
SSPADD Register ........................................................ 16, 17
SSPBUF ....................................................................... 17, 72
SSPBUF Register .............................................................. 15
SSPCON Register ............................................................. 15
SSPCON1 .................................................................... 65, 71
SSPCON2 .......................................................................... 66
SSPEN ............................................................................... 65
SSPIF ........................................................................... 22, 73
SSPM3:SSPM0 .................................................................. 65
SSPOV ................................................................... 65, 72, 83
SSPSTAT ..................................................................... 64, 72
SSPSTAT Register ...................................................... 16, 17
Stack .................................................................................. 26
Overflows ................................................................... 26
Underflow ................................................................... 26
Start bit (S) ......................................................................... 64
Start Condition Enabled bit ................................................ 66
STATUS Register ........................................................ 17, 18
C Bit ........................................................................... 18
DC Bit ......................................................................... 18
IRP Bit ........................................................................ 18
PD Bit ................................................................. 18, 125
RP1:RP0 Bits ............................................................. 18
TO Bit ................................................................. 18, 125
Z Bit ............................................................................ 18
Stop bit (P) ......................................................................... 64
Stop Condition Enable bit .................................................. 66
Synchronous Serial Port .................................................... 63
Synchronous Serial Port Enable bit, SSPEN ..................... 65
Synchronous Serial Port Interrupt ...................................... 22
Synchronous Serial Port Mode Select bits,
External Clock ................................................... 48
Interrupt ............................................................. 47
Prescaler ........................................................... 48
Prescaler Block Diagram ................................... 47
Section .............................................................. 47
T0CKI ................................................................ 48
Timer1
Asynchronous Counter Mode ............................ 53
Capacitor Selection ........................................... 53
Operation in Timer Mode ................................... 52
Oscillator ............................................................ 53
Prescaler ........................................................... 53
Resetting of Timer1 Registers ........................... 53
Resetting Timer1 using a CCP Trigger Output .. 53
Synchronized Counter Mode ............................. 52
T1CON .............................................................. 51
TMR1H .............................................................. 53
TMR1L ............................................................... 53
Timer2
Block Diagram ................................................... 55
Postscaler .......................................................... 55
Prescaler ........................................................... 55
T2CON .............................................................. 55
Timing Diagrams
A/D Conversion ....................................................... 172
Acknowledge Sequence Timing ................................ 85
Baud Rate Generator with Clock Arbitration .............. 78
BRG Reset Due to SDA Collision .............................. 90
Brown-out Reset ...................................................... 162
Bus Collision
Start Condition Timing ....................................... 89
Bus Collision During a Restart Condition (Case 1) .... 91
Bus Collision During a Restart Condition (Case2) ..... 91
Bus Collision During a Start Condition (SCL = 0) ...... 90
Bus Collision During a Stop Condition ....................... 92
Bus Collision for Transmit and Acknowledge ............ 88
Capture/Compare/PWM .......................................... 164
CLKOUT and I/O ..................................................... 161
SSPM3:SSPM0 .................................................................. 65
T
T1CKPS0 bit ...................................................................... 51
T1CKPS1 bit ...................................................................... 51
T1CON ............................................................................... 17
T1CON Register .......................................................... 17, 51
T1OSCEN bit ..................................................................... 51
T1SYNC bit ........................................................................ 51
T2CKPS0 bit ...................................................................... 55
T2CKPS1 bit ...................................................................... 55
T2CON Register .......................................................... 17, 55
TAD ................................................................................... 116
Timer0
Clock Source Edge Select (T0SE Bit) ........................ 19
Clock Source Select (T0CS Bit) ................................. 19
Overflow Enable (T0IE Bit) ........................................ 20
Overflow Flag (T0IF Bit) ..................................... 20, 132
Overflow Interrupt .................................................... 132
RA4/T0CKI Pin, External Clock ............................... 7, 8
Timer1 ................................................................................ 51
RC0/T1OSO/T1CKI Pin ........................................... 7, 8
RC1/T1OSI/CCP2 Pin .............................................. 7, 8
2
I C Bus Data ............................................................ 169
I C Bus Start/Stop bits ............................................. 168
I C Master Mode First Start bit timing ....................... 79
I C Master Mode Reception timing ............................ 84
2
2
2
2
I C Master Mode Transmission timing ...................... 82
Master Mode Transmit Clock Arbitration ................... 87
Power-up Timer ....................................................... 162
Repeat Start Condition .............................................. 80
Reset ....................................................................... 162
SPI Master Mode ....................................................... 68
SPI Slave Mode (CKE = 1) ........................................ 69
SPI Slave Mode Timing (CKE = 0) ............................ 69
Start-up Timer .......................................................... 162
Stop Condition Receive or Transmit .......................... 86
Time-out Sequence on Power-up .................... 129, 130
Timer0 ..................................................................... 163
Timer1 ..................................................................... 163
USART Asynchronous Master Transmission .......... 100
USART Asynchronous Reception ........................... 101
USART Synchronous Receive ................................ 170
USART Synchronous Reception ............................. 107
USART Synchronous Transmission ................ 106, 170
USART, Asynchronous Reception .......................... 104
Wake-up from SLEEP via Interrupt ......................... 135
Watchdog Timer ...................................................... 162
1999 Microchip Technology Inc.
DS30292B-page 189
MICROCHIP [ MICROCHIP ]
