PIC16C62X
FIGURE 9-17: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-6)
0
M
U
X
Postscaler
8
1
Watchdog
Timer
•
PS<2:0>
To TMR0 (Figure 6-6)
PSA
8 - to -1 MUX
PSA
WDT
Enable Bit
•
1
0
MUX
WDT
Time-out
Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
TABLE 9-9:
Address
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
81h
Config. bits
OPTION
---
BOREN
INTEDG
CP1
CP0
PWRTE
PSA
WDTE
PS2
FOSC1
PS1
FOSC0
PS0
RBPU
T0CS
T0SE
Legend: Shaded cells are not used by the Watchdog Timer.
_
Note:
= Unimplemented location, read as “0”
+ = Reserved for future use
DS30235G-page 58
Preliminary
1998 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
