PIC16F870/871
FIGURE 14-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
121
Pin
121
RC7/RX/DT
Pin
120
122
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-7: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param Sym
No.
Characteristic
Min
Typ† Max Units Conditions
Standard(F)
120
TckH2dtV
SYNC XMIT (MASTER &
SLAVE)
—
—
—
—
—
—
—
—
—
—
—
—
80
100
45
ns
ns
ns
ns
ns
ns
Clock high to data out valid
Extended(LF)
121
122
Tckrf
Tdtrf
Clock out rise time and fall time Standard(F)
(Master Mode)
Extended(LF)
50
Data out rise time and fall time Standard(F)
Extended(LF)
45
50
†:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 14-12: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
125
pin
RC7/RX/DT
pin
126
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-8: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
125
TdtV2ckL
TckL2dtl
SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time)
15
—
—
—
—
ns
ns
126
Data hold after CK ↓ (DT hold time)
15
†:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30569A-page 132
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
