PIC16F870/871
FIGURE 14-10: PARALLEL SLAVE PORT TIMING (PIC16F871 ONLY)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 14-3 for load conditions.
TABLE 14-6: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F871 ONLY)
Parameter
No.
Sym
Characteristic
Min Typ† Max Units Conditions
62
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
20
25
—
—
—
—
ns
ns
Extended
Range Only
63*
64
TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time) Standard(F)
Extended(LF)
20
35
—
—
—
—
ns
ns
TrdL2dtV RD↓ and CS↓ to data–out valid
—
—
—
—
80
90
ns
ns
Extended
Range Only
65
TrdH2dtI RD↑ or CS↓ to data–out invalid
10
—
30
ns
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1999 Microchip Technology Inc.
Preliminary
DS30569A-page 131
MICROCHIP [ MICROCHIP ]
