PIC16F7X7
TABLE 4-4:
CLOCK SWITCHING MODES
Current
System
Clock
New
System
Clock
SCS bits<1:0>
Modified to:
OSTS IOFS T1RUN
Delay
Comments
bit
bit
bit
LP, XT, HS,
T1OSC,
10
(INTRC)
8 Clocks of
INTRC
0
1(1)
0
INTRC
or
The internal RC oscillator
frequency is dependant upon
EC, RC
FOSC<2:0> = LP,
XT or HS
INTOSC the IRCF bits.
or
INTOSC
Postscaler
LP, XT, HS,
INTRC,
EC, RC
01
(T1OSC)
FOSC<2:0> = LP,
XT or HS
8 Clocks of
T1OSC
0
1
1
N/A
N/A
N/A
1
0
0
T1OSC T1OSCEN bit must be enabled.
INTRC
T1OSC
00
8 Clocks of
EC
or
RC
FOSC<2:0> = EC
or
FOSC<2:0> = RC
EC
or
RC
INTRC
T1OSC
00
1024 Clocks
+
8 Clocks of
LP, XT, HS
LP, XT, HS During the 1024 clocks,
program execution is clocked
from the secondary oscillator
until the primary oscillator
becomes stable.
FOSC<2:0> = LP,
XT, HS
LP, XT, HS
00
1024 Clocks
1
N/A
0
LP, XT, HS When a Reset occurs, there is
no clock transition sequence.
Instruction
(Due to Reset)
LP, XT, HS
execution and/or peripheral
operation is suspended unless
Two-Speed Start-up mode is
enabled, after which the INTRC
will act as the system clock
until the Oscillator Start-up
Timer has expired.
Note 1: If the new clock source is the INTOSC or INTOSC postscaler, then the IOFS bit will be set 4 ms (approx.)
after the clock change.
2004 Microchip Technology Inc.
DS30498C-page 47
MICROCHIP [ MICROCHIP ]
