PIC16F7X7
TABLE 4-4:
Current
System
Clock
CLOCK SWITCHING MODES
SCS bits<1:0>
Modified to:
Delay
8 Clocks of
INTRC
OSTS
bit
0
IOFS T1RUN
bit
bit
1
(1)
0
New
System
Clock
Comments
LP, XT, HS,
10
T1OSC,
(INTRC)
EC, RC
FOSC<2:0> = LP,
XT or HS
INTRC
The internal RC oscillator
or
frequency is dependant upon
INTOSC the IRCF bits.
or
INTOSC
Postscaler
T1OSC
T1OSCEN bit must be enabled.
LP, XT, HS,
01
INTRC,
(T1OSC)
EC, RC
FOSC<2:0> = LP,
XT or HS
INTRC
T1OSC
00
FOSC<2:0> = EC
or
FOSC<2:0> = RC
00
FOSC<2:0> = LP,
XT, HS
8 Clocks of
T1OSC
0
N/A
1
8 Clocks of
EC
or
RC
1024 Clocks
+
8 Clocks of
LP, XT, HS
1024 Clocks
1
N/A
0
EC
or
RC
LP, XT, HS During the 1024 clocks,
program execution is clocked
from the secondary oscillator
until the primary oscillator
becomes stable.
LP, XT, HS When a Reset occurs, there is
no clock transition sequence.
Instruction
execution and/or peripheral
operation is suspended unless
Two-Speed Start-up mode is
enabled, after which the INTRC
will act as the system clock
until the Oscillator Start-up
Timer has expired.
INTRC
T1OSC
1
N/A
0
LP, XT, HS
00
(Due to Reset)
LP, XT, HS
1
N/A
0
Note 1:
If the new clock source is the INTOSC or INTOSC postscaler, then the IOFS bit will be set 4 ms (approx.)
after the clock change.
2004 Microchip Technology Inc.
DS30498C-page 47
MICROCHIP [ MICROCHIP TECHNOLOGY ]
