PIC16F7X7
• Clock before switch: One of INTOSC/INTOSC
postscaler (IRCF<2:0> ≠ 000)
1. IRCF bits are modified to a different INTOSC/
INTOSC postscaler frequency.
4.6.5
CLOCK TRANSITION SEQUENCE
The following are three different sequences for
switching the internal RC oscillator frequency:
• Clock before switch: 31.25 kHz
(IRCF<2:0> = 000)
2. The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
1. IRCF bits are modified to an INTOSC/INTOSC
postscaler frequency.
3. The clock switching circuitry then waits for
eight falling edges of requested clock, after
which it switches CLKO to this new clock
source.
2. The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3. The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
4. The IOFS bit is set.
5. Oscillator switchover is complete.
4. The IOFS bit is clear to indicate that the clock is
unstable and a 4 ms (approx.) delay is started.
Time dependent code should wait for IOFS to
become set.
4.6.6
OSCILLATOR DELAY UPON
POWER-UP, WAKE-UP AND CLOCK
SWITCHING
Table 4-3 shows the different delays invoked for
various clock switching sequences. It also shows the
delays invoked for POR and wake-up.
5. Switchover is complete.
• Clock before switch: One of INTOSC/INTOSC
postscaler (IRCF<2:0> ≠ 000)
1. IRCF
bits
are
modified
to
INTRC
(IRCF<2:0> = 000).
2. The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3. The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
4. Oscillator switchover is complete.
TABLE 4-3:
From
OSCILLATOR DELAY EXAMPLES
Clock Switch
Frequency
Oscillator Delay
Comments
To
INTRC
T1OSC
31.25 kHz
32.768 kHz
CPU Start-up(1)
Sleep/POR
INTOSC/INTOSC
Postscaler
4 ms (approx.) and
CPU Start-up(1)
Following a wake-up from Sleep mode
or POR, CPU start-up is invoked to
allow the CPU to become ready for
code execution.
125 kHz-8 MHz
DC – 20 MHz
INTRC/
Sleep
EC, RC
EC, RC
INTRC
(31.25 kHz)
DC – 20 MHz
Following a change from INTRC, the
OST count of 1024 cycles must occur.
Sleep
LP, XT, HS
32.768 kHz-20 MHz
125 kHz-8 MHz
1024 Clock Cycles
4 ms (approx.)
INTRC
(31.25 kHz)
INTOSC/INTOSC
Postscaler
Refer to Section 4.6.4 “Modifying the
IRCF Bits” for further details.
Note 1: The 5 µs-10 µs start-up delay is based on a 1 MHz system clock.
DS30498C-page 40
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
