PIC16F7X7
FIGURE 4-6:
PIC16F7X7 CLOCK DIAGRAM
CONFIG1 (FOSC2:FOSC0)
SCS<1:0> (T1OSC)
Primary Oscillator
OSC2
Sleep
LP, XT, HS, RC, EC
OSC1
Peripherals
Secondary Oscillator
T1OSC
T1OSO
To Timer1
OSCCON<6:4>
T1OSCEN
Enable
Oscillator
T1OSI
Internal Oscillator
CPU
8 MHz
111
110
101
4 MHz
2 MHz
Internal
Oscillator
Block
1 MHz
100
011
010
001
000
500 kHz
250 kHz
125 kHz
31.25 kHz
8 MHz
(INTOSC)
31.25 kHz
Source
31.25 kHz
(INTRC)
WDT, FSCM
If the IRCF bits are modified while the internal oscillator
is running at any other frequency than INTRC
(31.25 kHz, IRCF<2:0> ≠ 000), there is no need for a
4 ms (approx.) clock switch delay. The new INTOSC
frequency will be stable immediately after the eight
falling edges. The IOFS bit will remain set after clock
switching occurs.
4.6.4
MODIFYING THE IRCF BITS
The IRCF bits can be modified at any time regardless of
which clock source is currently being used as the
system clock. The internal oscillator allows users to
change the frequency during run time. This is achieved
by modifying the IRCF bits in the OSCCON register.
The sequence of events that occur after the IRCF bits
are modified is dependent upon the initial value of the
IRCF bits before they are modified. If the INTRC
(31.25 kHz, IRCF<2:0> = 000) is running and the IRCF
bits are modified to any other value than ‘000’, a 4 ms
(approx.) clock switch delay is turned on. Code execu-
tion continues at a higher than expected frequency
while the new frequency stabilizes. Time sensitive code
should wait for the IOFS bit in the OSCCON register to
become set before continuing. This bit can be
monitored to ensure that the frequency is stable before
using the system clock in time critical applications.
Note:
Caution must be taken when modifying the
IRCF bits using BCFor BSFinstructions. It
is possible to modify the IRCF bits to a
frequency that may be out of the VDD
specification range; for example:
VDD = 2.0V and IRCF = 111(8 MHz).
2004 Microchip Technology Inc.
DS30498C-page 39
MICROCHIP [ MICROCHIP ]
