PIC16F7X7
FIGURE 18-6:
CLKO AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKO
13
12
18
19
14
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
Note: Refer to Figure 18-4 for load conditions.
TABLE 18-5: CLKO AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units Conditions
10*
TOSH2CKL OSC1 ↑ to CLKO ↓
TOSH2CKH OSC1 ↑ to CLKO ↑
—
—
—
—
—
75
75
35
35
—
200
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns (Note 1)
ns
11*
12*
13*
14*
15*
16*
17*
18*
200
TCKR
TCKF
CLKO Rise Time
CLKO Fall Time
100
100
TCKL2IOV CLKO ↓ to Port Out Valid
TIOV2CKH Port In Valid before CLKO ↑
0.5 TCY + 20
TOSC + 200
—
—
—
TCKH2IOI
Port In Hold after CLKO ↑
0
—
TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid
—
100
—
255
—
TOSH2IOI
OSC1 ↑ (Q2 cycle) to
Port Input Invalid (I/O in
hold time)
PIC16F7X7
100
200
ns
PIC16LF7X7
—
—
ns
19*
20*
TIOV2OSH Port Input Valid to OSC1 ↑ (I/O in setup time)
0
—
—
10
—
10
—
—
—
—
40
ns
ns
ns
ns
ns
ns
ns
TIOR
Port Output Rise Time
Port Output Fall Time
INT pin High or Low Time
PIC16F7X7
PIC16LF7X7
PIC16F7X7
PIC16LF7X7
—
145
40
21*
TIOF
—
—
145
—
22††* TINP
23††* TRBP
TCY
TCY
RB7:RB4 Change INT High or Low Time
—
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
DS30498C-page 224
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
