PIC16F7X
When either the CS or RD pins are detected high, the
PORTD outputs are disabled, and the interrupt flag bit
PSPIF is set on the Q4 clock cycle following the next
Q2 cycle, indicating that the read is complete. OBF
remains low until firmware writes new data to PORTD.
4.6
Parallel Slave Port
The Parallel Slave Port (PSP) is not implemented on
the PIC16F73 or PIC16F76.
PORTD operates as an 8-bit wide Parallel Slave Port,
or Microprocessor Port, when control bit PSPMODE
(TRISE<4>) is set. In Slave mode, it is asynchronously
readable and writable by an external system using the
read control input pin RE0/RD, the write control input
pin RE1/WR, and the chip select control input pin
RE2/CS.
When not in PSP mode, the IBF and OBF bits are held
clear. Flag bit IBOV remains unchanged. The PSPIF bit
must be cleared by the user in firmware; the interrupt
can be disabled by clearing the interrupt enable bit
PSPIE (PIE1<7>).
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
bit PSPMODE enables port pin RE0/RD to be the RD
input, RE1/WR to be the WR input and RE2/CS to be
the CS (chip select) input. For this functionality, the cor-
responding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (i.e., set).
The A/D port configuration bits PCFG3:PCFG0
(ADCON1<3:0>) must be set to configure pins
RE2:RE0 as digital I/O.
FIGURE 4-8:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Data Bus
D
Q
WR
Port
RDx
pin
CK
TTL
Q
D
There are actually two 8-bit latches, one for data output
(external reads) and one for data input (external
writes). The firmware writes 8-bit data to the PORTD
output data latch and reads data from the PORTD input
data latch (note that they have the same address). In
this mode, the TRISD register is ignored, since the
external device is controlling the direction of data flow.
RD
Port
EN
EN
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
An external write to the PSP occurs when the CS and
WR lines are both detected low. Firmware can read the
actual data on the PORTD pins during this time. When
either the CS or WR lines become high (level trig-
gered), the data on the PORTD pins is latched, and the
Input Buffer Full (IBF) status flag bit (TRISE<7>) and
interrupt flag bit PSPIF (PIR1<7>) are set on the Q4
clock cycle, following the next Q2 cycle to signal the
write is complete (Figure 4-9). Firmware clears the IBF
flag by reading the latched PORTD data, and clears the
PSPIF bit.
Read
RD
CS
WR
TTL
Chip Select
TTL
Write
TTL
Note: I/O pin has protection diodes to VDD and VSS.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE<5>) is set if an external write to the PSP occurs
while the IBF flag is set from a previous external write.
The previous PORTD data is overwritten with the new
data. IBOV is cleared by reading PORTD and clearing
IBOV.
A read from the PSP occurs when both the CS and RD
lines are detected low. The data in the PORTD output
latch is output to the PORTD pins. The Output Buffer
Full (OBF) status flag bit (TRISE<6>) is cleared imme-
diately (Figure 4-10), indicating that the PORTD latch is
being read, or has been read by the external bus. If
firmware writes new data to the output latch during this
time, it is immediately output to the PORTD pins, but
OBF will remain cleared.
DS30325B-page 40
2002 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
