PIC16F7X
FIGURE 4-7:
PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
4.5
PORTE and TRISE Register
This section is not applicable to the PIC16F73 or
PIC16F76.
Data Bus
WR Port
D
Q
PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configureable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
I/O pin(1)
CK
Data Latch
D
Q
I/O PORTE becomes control inputs for the micro-
processor port when bit PSPMODE (TRISE<4>) is set.
In this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). Ensure ADCON1 is configured for digital I/O. In
this mode, the input buffers are TTL.
WR TRIS
RD TRIS
Schmitt
Trigger
Input
CK
TRIS Latch
Buffer
Register 4-1 shows the TRISE register, which also con-
trols the parallel slave port operation.
Q
D
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as ’0’s.
EN
EN
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as ‘0’.
2002 Microchip Technology Inc.
DS30325B-page 37
MICROCHIP [ MICROCHIP ]
