PIC16F7X
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on:
POR,
BOR
Details
on page
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 1
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
27, 96
80h
81h
OPTION_REG RBPU
INTEDG
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect data memory address pointer
PORTA Data Direction Register
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 20, 44, 96
(4)
PCL
0000 0000
0001 1xxx
26, 96
19, 96
82h
(4)
STATUS
PD
Z
DC
C
83h
(4)
FSR
xxxx xxxx
--11 1111
1111 1111
1111 1111
1111 1111
27, 96
32, 96
34, 96
35, 96
36, 96
84h
85h
86h
87h
TRISA
TRISB
TRISC
TRISD
—
—
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
(5)
88h
(5)
TRISE
IBF
—
OBF
—
IBOV
—
PSPMODE
—
PORTE Data Direction Bits
0000 -111
---0 0000
0000 000x
38, 96
21, 96
23, 96
89h
(1,4)
PCLATH
INTCON
Write Buffer for the upper 5 bits of the Program Counter
8Ah
(4)
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
8Bh
(3)
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
PIE1
PIE2
PCON
—
ADIE
—
RCIE
—
TXIE
—
SSPIE
—
CCP1IE
TMR2IE
—
TMR1IE 0000 0000
CCP2IE ---- ---0
22, 96
24, 97
25, 97
—
PSPIE
—
—
—
—
—
—
—
—
POR
BOR
---- --qq
Unimplemented
—
—
—
Unimplemented
—
—
Unimplemented
—
—
PR2
SSPADD
Timer2 Period Register
1111 1111
0000 0000
52, 97
68, 97
2
Synchronous Serial Port (I C mode) Address Register
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
60, 97
—
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
TXSTA
SPBRG
—
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
69, 97
71, 97
Baud Rate Generator Register
Unimplemented
0000 0000
—
—
—
—
—
—
Unimplemented
—
Unimplemented
—
Unimplemented
—
Unimplemented
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0 -----000
84, 97
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (CALLor GOTO).
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
2002 Microchip Technology Inc.
DS30325B-page 17
MICROCHIP [ MICROCHIP ]
