PIC16F7X
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Value on:
POR,
BOR
Details
on page
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
27, 96
45, 96
26, 96
00h
01h
TMR0
PCL
Timer0 Module Register
xxxx xxxx
0000 0000
(4)
Program Counter (PC) Least Significant Byte
02h
(4)
STATUS
IRP
Indirect Data Memory Address Pointer
PORTA Data Latch when written: PORTA pins when read
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
19, 96
27, 96
03h
(4)
FSR
04h
05h
06h
07h
PORTA
PORTB
PORTC
PORTD
—
—
--0x 0000
xxxx xxxx
xxxx xxxx
32, 96
34, 96
35, 96
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
(5)
xxxx xxxx
---- -xxx
---0 0000
0000 000x
36, 96
39, 96
26, 96
21, 96
23, 96
08h
(5)
PORTE
PCLATH
INTCON
—
—
—
—
—
—
—
—
RE2
RE1
RE0
09h
(1,4)
Write Buffer for the upper 5 bits of the Program Counter
0Ah
(4)
GIE
PEIE
ADIF
—
TMR0IE
RCIF
—
INTE
TXIF
—
RBIE
SSPIF
—
TMR0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
0Bh
(3)
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
PIR1
TMR1IF 0000 0000
PSPIF
PIR2
—
CCP2IF ---- ---0
xxxx xxxx
24, 96
50, 96
50, 96
47, 96
52, 96
52, 96
TMR1L
TMR1H
T1CON
TMR2
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000
Timer2 Module Register
0000 0000
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
—
TOUTPS3 TOUTPS2 TOUTPS TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx 64, 68, 96
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000
61, 96
56, 96
56, 96
54, 96
70, 96
74, 96
76, 96
58, 96
58, 96
54, 96
88, 96
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx
xxxx xxxx
—
—
CCP1X
SREN
CCP1Y
CREN
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000
SPEN
RX9
—
FERR
OERR
RX9D
0000 -00x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
USART Transmit Data Register
USART Receive Data Register
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
—
—
CCP2X
CCP2Y
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000
A/D Result Register Byte
xxxx xxxx
GO/
DONE
1Fh
ADCON0
ADCS1 ADCS0
CHS2
CHS1
CHS0
—
ADON
0000 00-0
83, 96
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (CALLor GOTO).
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
DS30325B-page 16
2002 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
