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PIC16F628-04/SS 参数 Datasheet PDF下载

PIC16F628-04/SS图片预览
型号: PIC16F628-04/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 基于闪存的8位CMOS微控制器 [FLASH-Based 8-Bit CMOS Microcontrollers]
分类和应用: 闪存微控制器
文件页数/大小: 160 页 / 1657 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F62X  
14.2.6 INTERNAL 4 MHZ OSCILLATOR  
14.4  
Reset  
The internal RC oscillator provides a fixed 4 MHz (nom-  
inal) system clock at Vdd = 5V and 25°C, see “Electrical  
Specifications” section for information on variation over  
voltage and temperature.  
The PIC16F62X differentiates between various kinds  
of reset:  
a) Power-on reset (POR)  
b) MCLR reset during normal operation  
c) MCLR reset during SLEEP  
d) WDT reset (normal operation)  
e) WDT wake-up (SLEEP)  
14.2.7 CLKOUT  
The PIC16F62X can be configured to provide a clock  
out signal by programming the configuration word. The  
oscillator frequency, divided by 4 can be used for test  
purposes or to synchronize other logic.  
f) Brown-out Detect (BOD)  
Some registers are not affected in any reset condition;  
their status is unknown on POR and unchanged in any  
other reset. Most other registers are reset to a “reset  
state” on Power-on reset, MCLR reset, WDT reset and  
MCLR reset during SLEEP. They are not affected by a  
WDT wake-up, since this is viewed as the resumption  
of normal operation. TO and PD bits are set or cleared  
differently in different reset situations as indicated in  
Table 14-4. These bits are used in software to deter-  
mine the nature of the reset. See Table 14-7 for a full  
description of reset states of all registers.  
14.3  
Special Feature: Dual Speed  
Oscillator Modes  
A software programmable dual speed oscillator mode  
is provided when the PIC16F62X is configured in either  
ER or INTRC oscillator modes. This feature allows  
users to dynamically toggle the oscillator speed  
between 4MHz and 37kHz. In ER mode, the 4MHz set-  
ting will vary depending on the size of the external  
resistor. Also in ER mode, the 37kHz operation is fixed  
and does not vary with resistor size. Applications that  
require low current power savings, but cannot tolerate  
putting the part into sleep, may use this mode.  
A simplified block diagram of the on-chip reset circuit is  
shown in Figure 14-8.  
The MCLR reset path has a noise filter to detect and  
ignore small pulses. See Table 12-6 for pulse width  
specification.  
The OSCF bit in the PCON register is used to control  
dual speed mode. See Section 4.2.2.6, Figure 4-9.  
1999 Microchip Technology Inc.  
Preliminary  
DS40300B-page 99  
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