PIC16F62X
FIGURE 5-1: BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
FIGURE 5-2: BLOCK DIAGRAM OF
RA2/VREF PIN
Data
Bus
Data
Bus
D
Q
Q
D
Q
Q
VDD
VDD
VDD
P
VDD
P
WR
PORTA
WR
PORTA
CK
Data Latch
CK
Data Latch
D
Q
D
Q
RA2 Pin
I/O Pin
N
N
WR
WR
TRISA
TRISA
CK
Q
CK
TRIS Latch
Q
VSS
VSS
VSS
TRIS Latch
VSS
Analog
Input Mode
Analog
Input Mode
Schmitt Trigger
Input Buffer
Schmitt Trigger
Input Buffer
RD TRISA
RD TRISA
Q
D
Q
D
EN
EN
RD PORTA
RD PORTA
To Comparator
VROE
To Comparator
VREF
DS40300B-page 28
Preliminary
1999 Microchip Technology Inc.