PIC16F62X
4.2.2
SPECIAL FUNCTION REGISTERS
The special registers can be classified into two sets
(core and peripheral). The special function registers
associated with the “core” functions are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
The special function registers are registers used by the
CPU and Peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
TABLE 4-1:
SPECIAL REGISTERS SUMMARY BANK0
Value on
all other
Value on
POR
Reset
Address
Bank 0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
Resets
00h
01h
02h
03h
INDF
TMR0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s Register
xxxx xxxx xxxx xxxx
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
PCL
Program Counter's (PC) Least Significant Byte
STATUS
RP0
TO
PD
Z
DC
C
IRP
RP1
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
FSR
Indirect data memory address pointer
xxxx xxxx uuuu uuuu
xxxx 0000 xxxx 0000
xxxx xxxx uuuu uuuu
PORTA
RA7
RB7
RA6
RB6
RA5
RB5
RA4
RB4
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0
PORTB
Unimplemented
Unimplemented
Unimplemented
PCLATH
—
—
—
—
—
—
—
—
—
Write buffer for upper 5 bits of program counter
---0 0000 ---0 0000
0000 000x 0000 000u
0000 -000 0000 -000
INTCON
GIE
PEIE
CMIF
T0IE
INTE
TXIF
RBIE
T0IF
INTF
RBIF
PIR1
EEIF
RCIF
—
CCP1IF
TMR2IF
TMR1IF
Unimplemented
TMR1L
—
—
Holding register for the least significant byte of the 16-bit TMR1
Holding register for the most significant byte of the 16-bit TMR1
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR1H
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
TMR2
TMR2 module’s register
0000 0000 0000 0000
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -uuu uuuu
Unimplemented
Unimplemented
CCPR1L
—
—
—
—
Capture/Compare/PWM register (LSB)
Capture/Compare/PWM register (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCPR1H
CCP1CON
RCSTA
—
—
CCP1X
SREN
CCP1Y
CREN
CCP1M3
ADEN
CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
SPEN
RX9
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
TXREG
USART Transmit data register
USART Receive data register
RCREG
Unimplemented
Unimplemented
Unimplemented
Unimplemented
CMCON
—
—
—
—
—
—
—
—
C2OUT C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000 0000 0000
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during
normal operation.
1999 Microchip Technology Inc.
Preliminary
DS40300B-page 15
MICROCHIP [ MICROCHIP ]
