PIC16F870/871
.
2.2.2.7
PIR2 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The PIR2 Register contains the flag bit for the
EEPROM write operation interrupt.
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
EEIF
—
—
—
—
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n= Value at POR reset
bit 7-5: Unimplemented: Read as '0'
bit 4: EEIF: EEPROM Write Operation Interrupt Flag bit
1= The write operation completed (must be cleared in software)
0= The write operation is not complete or has not been started
bit 3-0: Unimplemented: Read as '0'
DS30569A-page 22
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
