PIC16F870/871
2.2.2.5
PIR1 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt bits are clear prior to enabling an
interrupt.
The PIR1 Register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
R/W-0
R-0
R-0
U-0
R/W-0
R/W-0
R/W-0
PSPIF(1) ADIF
RCIF
TXIF
CCP1IF TMR2IF TMR1IF
bit0
R = Readable bit
W = Writable bit
- n= Value at POR reset
bit7
(1)
bit 7:
bit 6:
bit 5:
bit 4:
PSPIF : Parallel Slave Port Read/Write Interrupt Flag bit
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed
0= The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer is full
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer is empty
0= The USART transmit buffer is full
bit 7:
Unimplemented: Read as ‘0’
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
bit 0:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Note 1: PSPIF is reserved on the PIC16F870; always maintain this bit clear.
DS30569A-page 20
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
