PIC16C745/765
ratio of up to 1:128 can be assigned to the WDT under
software control by writing to the OPTION register.
Time-out periods up to 128 TWDT can be realized.
13.8
Watchdog Timer (WDT)
The watchdog timer is a free running on-chip dedicated
oscillator, which does not require any external compo-
nents. The WDT will run, even if the clock on the OSC1/
CLKIN and OSC2/CLKOUT pins of the device has
been stopped, for example, by execution of a SLEEP
instruction.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT. In addition,
the SLEEPinstruction prevents the WDT from generat-
ing a reset, but will allow the WDT to wake the device
from sleep mode.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and resume normal operation (Watchdog
Timer Wake-up).
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
13.8.2 WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 13.1).
13.8.1 WDT PERIOD
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
The WDT has a nominal time-out period of 18 ms
(parameter #31, TWDT). The time-out periods vary with
temperature, VDD and process variations. If longer
time-out periods are desired, a prescaler with a division
FIGURE 13-7: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-1)
0
Postscaler
8
M
1
U
WDT Timer
X
8 - to - 1 MUX
PS<2:0>
PSA
WDT
Enable Bit
To TMR0 MUX
(Figure 6-1)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS<2:0> are bits in the OPTION register.
TABLE 13-8: SUMMARY OF WATCHDOG TIMER REGISTERS
Value on
All Other
Resets
Value on
POR, BOR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
(1)
2007h
Config. bits
—
BODEN
CP1
CP0 PWRTE
PSA
WDTE PLL FOSC0
PS2 PS1 PS0
81h,181h OPTION_REG
RBPU
INTEDG
T0CS T0SE
1111 1111 1111 1111
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 13-1 for operation of these bits.
DS41124A-page 106
Advanced Information
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
