PIC16C745/765
13.6.1 INT INTERRUPT
13.7
Context Saving During Interrupts
The external interrupt on RB0/INT pin is edge trig-
gered: either rising, if bit INTEDG (OPTION_REG<6>)
is set or falling, if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 13.9 for details on SLEEP mode.
During an interrupt, only the PC is saved on the stack.
At the very least, W and STATUS should be saved to
preserve the context for the interrupted program. All
registers that may be corrupted by the ISR, such as
PCLATH or FSR, should be saved.
Example 13-1 stores and restores the STATUS, W and
PCLATH registers. The register, W_TEMP, is defined in
Common RAM, the last 16 bytes of each bank that may
be accessed from any bank. The STATUS_TEMP and
PCLATH_TEMP are defined in bank 0.
The example:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Stores the PCLATH register in bank 0.
d) Executes the ISR code.
13.6.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 6.0)
e) Restores the PCLATH register.
f) Restores the STATUS register
g) Restores W.
13.6.3 PORTB INTERRUPT ON CHANGE
Note
that
W_TEMP,
STATUS_TEMP
and
PCLATH_TEMP are defined in the common RAM area
(70h - 7Fh) to avoid register bank switching during con-
text save and restore.
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 5.2)
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
EXAMPLE 13-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
#define
#define
#define
org
W_TEMP
0x70
0x71
0x72
STATUS_TEMP
PCLATH_TEMP
0x04
; start at Interrupt Vector
; Save W register
MOVWF
W_TEMP
MOVF
MOVWF
MOVF
MOVWF
:
STATUS,W
STATUS_TEMP
PCLATH,W
PCLATH_TEMP
; save STATUS
; save PCLATH
(Interrupt Service Routine)
:
MOVF
MOVWF
MOVF
MOVWF
SWAPF
SWAPF
RETFIE
PCLATH_TEMP,W
PCLATH
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
;
; swapf loads W without affecting STATUS flags
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 105
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