PIC16F7X
The sequence of events for 10-bit address is as fol-
lows, with steps 7 - 9 for slave-transmitter:
9.3.1.1
Addressing
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
1. Receive first (high) byte of address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF, and UA are set).
a) The SSPSR register value is loaded into the
SSPBUF register.
5. Update the SSPADD register with the first (high)
byte of address, if match releases SCL line, this
will clear bit UA.
b) The buffer full bit, BF is set.
c) An ACK pulse is generated.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
7. Receive Repeated START condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
In 10-bit Address mode, two address bytes need to be
received by the slave (Figure 9-7). The five Most Sig-
nificant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the sec-
ond address byte. For a 10-bit address, the first byte
would equal ‘1111 0 A9 A8 0’, where A9and A8are
the two MSbs of the address.
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
TABLE 9-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
Set bit SSPIF
Generate ACK
(SSP Interrupt occurs
Pulse
SSPSR → SSPBUF
if enabled)
BF
SSPOV
0
1
1
0
0
0
1
1
Yes
No
No
No
Yes
No
No
No
Yes
Yes
Yes
Yes
Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
9.3.1.2
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set. This is an error
condition due to the user’s firmware.
DS30325B-page 66
2002 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
