PIC16F7X
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment, either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 5.2.
5.0
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler is not readable or writable. Section 5.3 details the
operation of the prescaler.
Additional information on the Timer0 module is avail-
able in the PICmicro™ Mid-Range MCU Family Refer-
ence Manual (DS33023).
5.1
Timer0 Interrupt
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
TMR0IF (INTCON<2>). The interrupt can be masked
by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF
must be cleared in software by the Timer0 module
Interrupt Service Routine, before re-enabling this inter-
rupt. The TMR0 interrupt cannot awaken the processor
from SLEEP, since the timer is shut-off during SLEEP.
Timer0 operation is controlled through the
OPTION_REG register (Register 5-1 on the following
page). Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 5-1:
BLOCK DIAGRAM OF THE TIMER0 MODULE AND PRESCALER
Data Bus
CLKOUT (= FOSC/4)
8
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
pin
SYNC
2
TMR0 reg
Cycles
T0SE
T0CS
Set Flag bit TMR0IF
PSA
on Overflow
PRESCALER
0
1
8-bit Prescaler
M
U
X
8
Watchdog
Timer
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
2002 Microchip Technology Inc.
DS30325B-page 43
MICROCHIP [ MICROCHIP ]
