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PIC16F73-I/SPG 参数 Datasheet PDF下载

PIC16F73-I/SPG图片预览
型号: PIC16F73-I/SPG
PDF下载: 下载PDF文件 查看货源
内容描述: [28 Pin, 7KB Std Flash, 192 RAM, 22 I/O, -40C to +85C, 28-SPDIP, TUBE]
分类和应用: 闪存微控制器
文件页数/大小: 174 页 / 3853 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F7X  
DECFSZ  
Decrement f, Skip if 0  
INCFSZ  
Increment f, Skip if 0  
Syntax:  
[ label ] DECFSZ f,d  
Syntax:  
[ label ] INCFSZ f,d  
Operands:  
0 f 127  
d [0,1]  
Operands:  
0 f 127  
d [0,1]  
Operation:  
(f) - 1 (destination);  
skip if result = 0  
Operation:  
(f) + 1 (destination),  
skip if result = 0  
Status Affected: None  
Status Affected: None  
Description:  
The contents of register fare  
Description:  
The contents of register fare  
decremented. If dis 0, the result  
is placed in the W register. If dis  
1, the result is placed back in  
register f.  
incremented. If dis 0, the result is  
placed in the W register. If dis 1,  
the result is placed back in  
register f.  
If the result is 1, the next instruc-  
tion is executed. If the result is 0,  
then a NOPis executed instead,  
making it a 2TCY instruction.  
If the result is 1, the next instruc-  
tion is executed. If the result is 0,  
a NOPis executed instead, making  
it a 2TCY instruction.  
GOTO  
Unconditional Branch  
IORLW  
Inclusive OR Literal with W  
Syntax:  
[ label ] GOTO k  
0 k 2047  
Syntax:  
[ label ] IORLW k  
0 k 255  
Operands:  
Operation:  
Operands:  
Operation:  
Status Affected:  
Description:  
k PC<10:0>  
PCLATH<4:3> PC<12:11>  
(W) .OR. k (W)  
Z
Status Affected: None  
The contents of the W register are  
ORed with the eight-bit literal 'k'.  
The result is placed in the W  
register.  
Description:  
GOTOis an unconditional branch.  
The eleven-bit immediate value is  
loaded into PC bits <10:0>. The  
upper bits of PC are loaded from  
PCLATH<4:3>. GOTOis a two-  
cycle instruction.  
IORWF  
Inclusive OR W with f  
INCF  
Increment f  
Syntax:  
[ label ] IORWF f,d  
Syntax:  
[ label ] INCF f,d  
Operands:  
0 f 127  
d [0,1]  
Operands:  
0 f 127  
d [0,1]  
Operation:  
(W) .OR. (f) (destination)  
Operation:  
(f) + 1 (destination)  
Status Affected:  
Description:  
Z
Status Affected:  
Description:  
Z
Inclusive OR the W register with  
register 'f'. If 'd' is 0, the result is  
placed in the W register. If 'd' is 1,  
the result is placed back in  
register 'f'.  
The contents of register fare  
incremented. If dis 0, the result  
is placed in the W register. If dis  
1, the result is placed back in  
register f.  
2002 Microchip Technology Inc.  
DS30325B-page 109  
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