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PIC16F73-I/SPG 参数 Datasheet PDF下载

PIC16F73-I/SPG图片预览
型号: PIC16F73-I/SPG
PDF下载: 下载PDF文件 查看货源
内容描述: [28 Pin, 7KB Std Flash, 192 RAM, 22 I/O, -40C to +85C, 28-SPDIP, TUBE]
分类和应用: 闪存微控制器
文件页数/大小: 174 页 / 3853 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F7X  
CALL  
Call Subroutine  
CLRWDT  
Clear Watchdog Timer  
Syntax:  
[ label ] CALL k  
0 k 2047  
Syntax:  
[ label ] CLRWDT  
Operands:  
Operation:  
Operands:  
Operation:  
None  
(PC)+ 1TOS,  
k PC<10:0>,  
(PCLATH<4:3>) PC<12:11>  
00h WDT  
0 WDT prescaler,  
1 TO  
1 PD  
Status Affected: None  
Status Affected: TO, PD  
Description:  
Call Subroutine. First, return  
address (PC+1) is pushed onto  
the stack. The eleven-bit immedi-  
ate address is loaded into PC bits  
<10:0>. The upper bits of the PC  
are loaded from PCLATH. CALLis  
a two-cycle instruction.  
Description:  
CLRWDTinstruction resets the  
Watchdog Timer. It also resets the  
prescaler of the WDT. Status bits  
TO and PD are set.  
CLRF  
Clear f  
COMF  
Complement f  
Syntax:  
[ label ] CLRF  
0 f 127  
f
Syntax:  
[ label ] COMF f,d  
Operands:  
Operation:  
Operands:  
0 f 127  
d [0,1]  
00h (f)  
1 Z  
Operation:  
(f) (destination)  
Status Affected:  
Description:  
Z
Status Affected:  
Description:  
Z
The contents of register fare  
cleared and the Z bit is set.  
The contents of register fare  
complemented. If dis 0, the  
result is stored in W. If dis 1, the  
result is stored back in register f.  
CLRW  
Clear W  
DECF  
Decrement f  
Syntax:  
[ label ] CLRW  
Syntax:  
[ label ] DECF f,d  
Operands:  
Operation:  
None  
Operands:  
0 f 127  
d [0,1]  
00h (W)  
1 Z  
Operation:  
(f) - 1 (destination)  
Status Affected:  
Description:  
Z
Status Affected:  
Description:  
Z
W register is cleared. Zero bit (Z)  
is set.  
Decrement register f. If dis 0,  
the result is stored in the W  
register. If dis 1, the result is  
stored back in register f.  
DS30325B-page 108  
2002 Microchip Technology Inc.