PIC16LC72-04/SS 参数 Datasheet PDF下载

PIC16C72 Series

TABLE 2-1

Address Name

SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on all

other resets

(3)

Bank 1

80h

(1)

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

(1,2)

(1)

(1)

(1)

(1)

INDF

OPTION_REG

PCL

STATUS

FSR

TRISA

TRISB

TRISC

—

—

PCLATH

INTCON

PIE1

—

PCON

—

—

—

PR2

SSPADD

SSPSTAT

—

—

—

—

—

—

—

—

—

—

ADCON1

Addressing this location uses contents of FSR to address data memory (not a physical register)

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

0000 0000 0000 0000

1111 1111 1111 1111

0000 0000 0000 0000

Program Counter's (PC) Least Significant Byte

IRP

(4)

RP1

(4)

RP0

TO

PD

Z

DC

C

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

--11 1111 --11 1111

1111 1111 1111 1111

1111 1111 1111 1111

—

—

—

—

Indirect data memory address pointer

—

—

PORTA Data Direction Register

PORTB Data Direction Register

PORTC Data Direction Register

Unimplemented

Unimplemented

—

GIE

—

—

PEIE

ADIE

—

T0IE

—

Write Buffer for the upper 5 bits of the PC

INTE

—

RBIE

SSPIE

T0IF

CCP1IE

INTF

TMR2IE

RBIF

TMR1IE

---0 0000 ---0 0000

0000 000x 0000 000u

-0-- 0000 -0-- 0000

—

—

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

Unimplemented

—

Unimplemented

Unimplemented

Unimplemented

Timer2 Period Register

Synchronous Serial Port (I

2

C mode) Address Register

SMP

(5)

CKE

(5)

D/A

P

S

R/W

UA

BF

—

—

—

—

—

POR

BOR

---- --qq ---- --uu

—

—

—

—

—

—

1111 1111 1111 1111

0000 0000 0000 0000

0000 0000 0000 0000

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

---- -000

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

Unimplemented

—

—

—

—

—

PCFG2

PCFG1

PCFG0

---- -000

Legend:

x

= unknown,

u

= unchanged,

q

= value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.

3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

4: The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear.

5: SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.

DS39016A-page 8

Preliminary

©

1998 Microchip Technology Inc.