PIC16C72 Series
2.2.2.4
PIE1 REGISTER
Note: Bit PEIE (INTCON<6>) must be set to
This register contains the individual enable bits for the
peripheral interrupts.
enable any peripheral interrupt.
FIGURE 2-6: PIE1 REGISTER (ADDRESS 8Ch)
U-0
—
R/W-0
ADIE
U-0
—
U-0
—
R/W-0
SSPIE
R/W-0
R/W-0
TMR2IE TMR1IE
bit0
R/W-0
CCP1IE
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
- n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6:
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5-4: Unimplemented: Read as '0'
bit 3:
bit 2:
bit 1:
bit 0:
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
DS39016A-page 12
Preliminary
1998 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
