PIC16C63A/65B/73B/74B
13.7.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken into account that under worst
case conditions (V
DD
= Min., Temperature = Max., and
max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.
Note:
When a
CLRWDT
instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
FIGURE 13-6:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
0
WDT Timer
1
M
U
X
Postscaler
8
8 - to - 1 MUX
WDT
Enable Bit
PSA
To TMR0 MUX (Figure 6-1)
0
MUX
1
PSA
PS2:PS0
WDT
Time-out
Note:
PSA and PS2:PS0 are bits in the OPTION register.
TABLE 13-7:
Address
2007h
81h
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
–
RBPU
Bit 6
BODEN
(1)
INTEDG
Bit 5
CP1
T0CS
Bit 4
CP0
T0SE
Bit 3
PWRTE
(1)
PSA
Bit 2
WDTE
PS2
Bit 1
FOSC1
PS1
Bit 0
FOSC0
PS0
Config. bits
OPTION_REG
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1:
See Register 13-1 for operation of these bits.
DS30605C-page 96
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
