PIC16C63A/65B/73B/74B
5.0
I/O PORTS
FIGURE 5-1:
Data
Bus
WR
Port
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
Q
V
DD
D
5.1
PORTA and TRISA Registers
CK
Q
P
I/O pin
(1)
PORTA is a 6-bit latch.
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL
input levels and full CMOS output drivers. All pins have
data direction bits (TRIS registers), which can config-
ure these pins as output or input.
Setting a TRISA register bit puts the corresponding out-
put driver in a hi-impedance mode. Clearing a bit in the
TRISA register puts the contents of the output latch on
the selected pin(s).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
On the PIC16C73B/74B, PORTA pins are multiplexed
with analog inputs and analog V
REF
input. The opera-
tion of each pin is selected by clearing/setting the con-
trol bits in the ADCON1 register (A/D Control
Register1).
Note:
On all RESETS, pins with analog functions
are configured as analog and digital inputs.
RD Port
Data Latch
D
WR
TRIS
Q
N
CK
Q
TRIS Latch
V
SS
Analog
Input
mode
RD TRIS
Q
D
TTL
Input
Buffer
EN
To A/D Converter
Note 1:
I/O pins have protection diodes to V
DD
and V
SS
.
FIGURE 5-2:
Data
Bus
WR
Port
BLOCK DIAGRAM OF
RA4/T0CKI PIN
D
Q
Q
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
CK
EXAMPLE 5-1:
BCF
CLRF
STATUS, RP0
PORTA
INITIALIZING PORTA
(PIC16C73B/74B)
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Data Latch
D
Q
Q
N
V
SS
Schmitt
Trigger
Input
Buffer
I/O pin
(1)
WR
TRIS
Initialize PORTA by
clearing output
data latches
Select Bank 1
Configure all pins
as digital inputs
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA<5:4> as outputs
TRISA<7:6> are always
read as ’0’.
CK
TRIS Latch
BSF
MOVLW
MOVWF
MOVLW
STATUS, RP0
0x06
ADCON1
0xCF
RD TRIS
Q
D
EN
EN
MOVWF
TRISA
RD Port
TMR0 Clock Input
Note 1:
I/O pins have protection diodes to V
DD
and V
SS
.
2000 Microchip Technology Inc.
DS30605C-page 29
MICROCHIP [ MICROCHIP TECHNOLOGY ]
