PIC16F872
REGISTER 4-1: EECON1 REGISTER (ADDRESS 18Ch)
R/W-x
EEPGD
bit7
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-0
—
—
—
WRERR WREN
WR
RD
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit0
- n= Value at POR reset
bit 7:
EEPGD: Program / Data EEPROM Select bit
1= Accesses Program memory
0= Accesses data memory
(This bit cannot be changed while a read or write operation is in progress)
bit 6-4: Unimplemented: Read as '0'
bit 3:
WRERR: EEPROM Error Flag bit
1= A write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
0= The write operation completed
bit 2:
bit 1:
WREN: EEPROM Write Enable bit
1= Allows write cycles
0= Inhibits write to the EEPROM
WR: Write Control bit
1= initiates a write cycle. (The bit is cleared by hardware once write is complete.) The WR bit can only
be set (not cleared) in software.
0= Write cycle to the EEPROM is complete
bit 0:
RD: Read Control bit
1= Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not cleared) in
software.
0= Does not initiate an EEPROM read
DS30221A-page 30
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
