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PIC16F872-I/SS 参数 Datasheet PDF下载

PIC16F872-I/SS图片预览
型号: PIC16F872-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28引脚, 8位CMOS闪存微控制器 [28-Pin, 8-Bit CMOS FLASH Microcontroller]
分类和应用: 闪存微控制器
文件页数/大小: 160 页 / 2454 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F872  
3.3  
PORTC and the TRISC Register  
FIGURE 3-6: PORTC BLOCK DIAGRAM  
(PERIPHERAL OUTPUT  
PORTC is an 8-bit wide, bi-directional port. The corre-  
sponding data direction register is TRISC. Setting a  
TRISC bit (=1) will make the corresponding PORTC pin  
an input (i.e., put the corresponding output driver in a  
hi-impedance mode). Clearing a TRISC bit (=0) will  
make the corresponding PORTC pin an output (i.e., put  
the contents of the output latch on the selected pin).  
OVERRIDE) RC<3:4>  
Port/Peripheral Select(2)  
Peripheral Data Out  
VDD  
0
Data Bus  
D
Q
Q
P
WR  
Port  
1
CK  
PORTC is multiplexed with several peripheral functions  
(Table 3-5). PORTC pins have Schmitt Trigger input  
buffers.  
When the I2C module is enabled, the PORTC (3:4) pins  
can be configured with normal I2C levels or with  
SMBUS levels by using the CKE bit (SSPSTAT<6>).  
Data Latch  
I/O  
pin(1)  
D
Q
Q
WR  
TRIS  
CK  
N
TRIS Latch  
Vss  
When enabling peripheral functions, care should be  
taken in defining TRIS bits for each PORTC pin. Some  
peripherals override the TRIS bit to make a pin an out-  
put, while other peripherals override the TRIS bit to  
make a pin an input. Since the TRIS bit override is in  
effect while the peripheral is enabled, read-modify-  
write instructions (BSF, BCF, XORWF) with TRISC as  
destination should be avoided. The user should refer to  
the corresponding peripheral section for the correct  
TRIS bit settings.  
Schmitt  
Trigger  
RD TRIS  
Peripheral  
OE(3)  
Q
D
Schmitt  
Trigger  
with  
SMBus  
levels  
EN  
RD  
Port  
0
SSPl Input  
1
CKE  
SSPSTAT<6>  
Note 1: I/O pins have diode protection to VDD and VSS.  
2: Port/Peripheral select signal selects between port  
data and peripheral output.  
FIGURE 3-5: PORTC BLOCK DIAGRAM  
(PERIPHERAL OUTPUT  
OVERRIDE) RC<0:2>  
RC<5:7>  
3: Peripheral OE (output enable) is only activated if  
peripheral select is active.  
Port/Peripheral Select(2)  
Peripheral Data Out  
VDD  
0
Data Bus  
D
Q
Q
P
WR  
Port  
1
CK  
Data Latch  
I/O  
pin(1)  
D
Q
Q
WR  
TRIS  
CK  
N
TRIS Latch  
VSS  
Schmitt  
Trigger  
RD TRIS  
Peripheral  
OE(3)  
Q
D
EN  
RD  
Port  
Peripheral Input  
Note 1: I/O pins have diode protection to VDD and VSS.  
2: Port/Peripheral select signal selects between port  
data and peripheral output.  
3: Peripheral OE (output enable) is only activated if  
peripheral select is active.  
1999 Microchip Technology Inc.  
Preliminary  
DS30221A-page 27  
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