PIC16F872
.
2.2.2.7
PIR2 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The PIR2 register contains the flag bits for the SSP bus
collision interrupt and the EEPROM write operation
interrupt.
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
U-0
R/W-0
U-0
R/W-0
R/W-0
U-0
U-0
R/W-0
—
—
—
EEIF
BCLIF
—
—
—
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n= Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
Unimplemented: Read as '0'
Reserved: Always maintain this bit clear
Unimplemented: Read as '0'
EEIF: EEPROM Write Operation Interrupt Flag bit
1= The write operation completed (must be cleared in software)
0= The write operation is not complete or has not been started
bit 3:
BCLIF: Bus Collision Interrupt Flag
1= A bus collision has occurred in the SSP, when configured for I2C master mode
0= No bus collision has occurred
bit 2-1: Unimplemented: Read as '0'
bit 0: Reserved: Always maintain this bit clear
DS30221A-page 18
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
